D. C. Wei, Y. Huang, B. W. Garlepp, J. Hein. A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 884-893, IEEE, 2006. [doi]
Abstract is missing.