Table of Contents

• General Chair's MessageHarry Foster. 1 [doi]
• HADFL: Heterogeneity-aware Decentralized Federated Learning FrameworkJing Cao, Zirui Lian, Weihong Liu, Zongwei Zhu, Cheng Ji. 1-6 [doi]
• Invited: Security Beyond Bulk Silicon: Opportunities and Challenges of Emerging DevicesLejla Batina, Rosario Cammarota, Nele Mentens, Ahmad-Reza Sadeghi, Johanna Sepúlveda, Shaza Zeitouni. 1-4 [doi]
• RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning SystemAlejandro Hernández-Cano, Cheng Zhuo, Xunzhao Yin, Mohsen Imani. 7-12 [doi]
• A3C-S: Automated Agent Accelerator Co-Search towards Efficient Deep Reinforcement LearningYonggan Fu, Yongan Zhang, Chaojian Li, Zhongzhi Yu, Yingyan Lin. 13-18 [doi]
• AID: Attesting the Integrity of Deep Neural NetworksOmid Aramoon, Pin-Yu Chen, Gang Qu. 19-24 [doi]
• MAT: Processing In-Memory Acceleration for Long-Sequence AttentionMinxuan Zhou, Yunhui Guo, Weihong Xu, Bin Li, Kevin W. Eliceiri, Tajana Rosing. 25-30 [doi]
• JPDHeap: A JVM Heap Design for PM-DRAM MemoriesLitong You, Tianxiao Gu, Shengan Zheng, Jianmei Guo, Sanhong Li, Yuting Chen, Linpeng Huang. 31-36 [doi]
• SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUsJianqi Zhao, Yao Wen, YuChen Luo, Zhou Jin, Weifeng Liu, Zhenya Zhou. 37-42 [doi]
• PIM-Quantifier: A Processing-in-Memory Platform for mRNA QuantificationFan Zhang, Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang, Deliang Fan. 43-48 [doi]
• Network-on-Interposer Design for Agile Neural-Network Processor Chip CustomizationMengdi Wang, Ying Wang, Cheng Liu, Lei Zhang. 49-54 [doi]
• Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoCYuan Zhou, Hanyu Wang, Jieming Yin, Zhiru Zhang. 55-60 [doi]
• Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-ChipAnup Gangwar, Ravishankar Sreedharan, Ambica Prasad, Nitin Kumar Agarwal, Sri Harsha Gade. 61-66 [doi]
• AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCsEbadollah Taheri, Ryan G. Kim, Mahdi Nikdast. 67-72 [doi]
• Quantifying Rowhammer Vulnerability for DRAM SecurityYichen Jiang, Huifeng Zhu, Dean Sullivan, Xiaolong Guo, Xuan Zhang 0001, Yier Jin. 73-78 [doi]
• HLock: Locking IPs at the High-Level LanguageMd Rafid Muttaki, Roshanak Mohammadivojdan, Mark Mohammad Tehranipoor, Farimah Farahmandi. 79-84 [doi]
• SACReD: An Attack Framework on SAC Resistant Delay-PUFs leveraging Bias and Reliability FactorsDurba Chatterjee, Urbi Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra. 85-90 [doi]
• Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided AttacksNimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri. 91-96 [doi]
• Move-On-Modify: An Efficient yet Crash-Consistent Update Strategy for Interlaced Magnetic RecordingYuhong Liang, Ming-Chang Yang. 97-102 [doi]
• Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMRYungang Pan, Zhiping Jia, Zhaoyan Shen, Bingzhe Li, Wanli Chang 0001, Zili Shao. 103-108 [doi]
• OpenMem: Hardware/Software Cooperative Management for Mobile Memory SystemFei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy. 109-114 [doi]
• MobileSwap: Cross-Device Memory Swapping for Mobile DevicesChanglong Li, Liang Shi, Chun Jason Xue. 115-120 [doi]
• Bayesian Inference Based Robust Computing on Memristor CrossbarDi Gao, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo. 121-126 [doi]
• Secure Logic Locking with Strain-Protected Nanomagnet LogicNaimul Hassan, Alexander J. Edwards, Dhritiman Bhattacharya, Mustafa M. Shihab, Varun Venkat, Peng Zhou, Xuan Hu, Shamik Kundu, Abraham Peedikayil Kuruvila, Kanad Basu, Jayasimha Atulasimha, Yiorgos Makris, Joseph S. Friedman. 127-132 [doi]
• qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ TechnologyGhasem Pasandi, Massoud Pedram. 133-138 [doi]
• Tamper-Resistant Optical Logic Circuits Based on Integrated NanophotonicsJun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi. 139-144 [doi]
• MyML: User-Driven Machine LearningVidushi Goyal, Valeria Bertacco, Reetuparna Das. 145-150 [doi]
• ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge SystemsShuo Huai, Lei Zhang, Di Liu, Weichen Liu, Ravi Subramaniam. 151-156 [doi]
• EImprove - Optimizing Energy and Comfort in Buildings based on Formal Semantics and Reinforcement LearningSagar Verma, Supriya Agrawal, R. Venkatesh 0001, Ulka Shrotri, Srinarayana Nagarathinam, Rajesh Jayaprakash, Aabriti Dutta. 157-162 [doi]
• Enabling On-Device Model Personalization for Ventricular Arrhythmias Detection by Generative Adversarial NetworksZhenge Jia, Feng Hong, Lichuan Ping, Yiyu Shi, Jingtong Hu. 163-168 [doi]
• Attentional Transfer is All You Need: Technology-aware Layout Pattern GenerationXiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young. 169-174 [doi]
• Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot DetectionBingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao-Wen Chang. 175-180 [doi]
• Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point RetrievalSean Shang-En Tseng, Iris Hui-Ru Jiang, James P. Shiely. 181-186 [doi]
• NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling SynthesisJunzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu 0001, Dian Zhou, Xuan Zeng 0001. 187-192 [doi]
• A Compute-in-Memory Architecture Compatible with 3D NAND Flash that Parallelly Activates Multi-LayersLiang Zhao, Chu Yan, Fan Yang, Shifan Gao, Gabriel Rosca, Dan Manea, Zhichao Lu, Yi Zhao. 193-198 [doi]
• Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-MemoryOrian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky. 199-204 [doi]
• GCiM: A Near-Data Processing Accelerator for Graph ConstructionLei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li 0001. 205-210 [doi]
• Max-PIM: Fast and Efficient Max/Min Searching in DRAMFan Zhang, Shaahin Angizi, Deliang Fan. 211-216 [doi]
• GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy DetectionRozhin Yasaei, Shih-Yuan Yu, Emad Kasaeyan Naeini, Mohammad Abdullah Al Faruque. 217-222 [doi]
• Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-SynthesisRajat Sadhukhan, Sayandeep Saha, Debdeep Mukhopadhyay. 223-228 [doi]
• Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic BlocksGaurav Kolhe, Soheil Salehi, Tyler David Sheaves, Houman Homayoun, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan. 229-234 [doi]
• A Resource Binding Approach to Logic ObfuscationMichael Zuzak, Yuntao Liu 0001, Ankur Srivastava. 235-240 [doi]
• An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load BalanceChangchun Zhou, Min Liu, Siyuan Qiu, Yifan He, Hailong Jiao. 241-246 [doi]
• Dataflow Mirroring: Architectural Support for Highly Efficient Fine-Grained Spatial Multitasking on Systolic-Array NPUsJounghoo Lee, Jinwoo Choi, Jaeyeon Kim, Jinho Lee, Youngsok Kim. 247-252 [doi]
• RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPUGeonhwa Jeong, Eric Qin 0001, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna. 253-258 [doi]
• FIXAR: A Fixed-Point Deep Reinforcement Learning Platform with Quantization-Aware Training and Adaptive ParallelismJe Yang, Seongmin Hong, Joo-Young Kim. 259-264 [doi]
• SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core ProcessorsMartin Rapp, Mohammed Bakr Sikal, Heba Khdr, Jörg Henkel. 265-270 [doi]
• 2 GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative AddersVijay Kandiah, Ali Murat Gök, Georgios Tziantzioulis, Nikos Hardavellas. 271-276 [doi]
• Synergically Rebalancing Parallel Execution via DCT and Turbo BoostingSandro M. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon. 277-282 [doi]
• SPROUT - Smart Power ROUting Tool for Board-Level Exploration and PrototypingRassul Bairamkulov, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas, Eby G. Friedman. 283-288 [doi]
• SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-VHsu-Kang Dow, Tuo Li 0001, William Miles, Sri Parameswaran. 289-294 [doi]
• DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGAYukui Luo, Cheng Gongye, Yunsi Fei, Xiaolin Xu. 295-300 [doi]
• SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous ArchitectureKe Xia, Yukui Luo, Xiaolin Xu, Sheng Wei 0001. 301-306 [doi]
• ROLoad: Securing Sensitive Operations with Pointee IntegrityWende Tan, Yuan Li, Chao Zhang, Xingman Chen, Songtao Yang, Ying Liu, Jianping Wu. 307-312 [doi]
• DIALED: Data Integrity Attestation for Low-end Embedded DevicesIvan De Oliveira Nunes, Sashidhar Jakkamsetti, Gene Tsudik. 313-318 [doi]
• Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault InjectionPantea Kiaei, Cees-Bart Breunesse, Mohsen Ahmadi, Patrick Schaumont, Jasper Van Woudenberg. 319-324 [doi]
• UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-GatingPramesh Pandey, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy. 325-330 [doi]
• Enabling the Design of Behavioral Systems-on-ChipSantosh Shetty, Benjamin Camon Schafer. 331-336 [doi]
• DANCE: Differentiable Accelerator/Network Co-ExplorationKanghyun Choi, Deokki Hong, Hojae Yoon, Joonsang Yu, Youngsok Kim, Jinho Lee. 337-342 [doi]
• New Regular Expressions on Old AcceleratorsJackson Woodruff, Michael F. P. O'Boyle. 343-348 [doi]
• Property-driven Automatic Generation of Reduced-ISA HardwareNathaniel Bleier, John Sartori, Rakesh Kumar. 349-354 [doi]
• BHDL: A Lucid, Expressive, and Embedded Programming Language and System for PCB DesignsHebi Li, Youbiao He, Qi Xiao, Jin Tian, Forrest Sheng Bao. 355-360 [doi]
• Neuromorphic Algorithm-hardware Codesign for Temporal Pattern LearningHaowen Fang, Brady Taylor, Ziru Li, Zaidao Mei, Hai Helen Li, Qinru Qiu. 361-366 [doi]
• In-Hardware Learning of Multilayer Spiking Neural Networks on a Neuromorphic ProcessorAmar Shrestha, Haowen Fang, Daniel Patrick Rider, Zaidao Mei, Qinru Qiu. 367-372 [doi]
• Noise-Robust Deep Spiking Neural Networks with Temporal InformationSeongsik Park, DongJin Lee, Sungroh Yoon. 373-378 [doi]
• SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAMRachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 379-384 [doi]
• Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based ImagersMaxence Bouvier, Alexandre Valentian, Gilles Sicard. 385-390 [doi]
• HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional ComputingDongning Ma, Jianmin Guo, Yu Jiang 0001, Xun Jiao. 391-396 [doi]
• Cocktail: Learn a Better Neural Network Controller from Multiple Experts via Adaptive Mixing and Robust DistillationYixuan Wang, Chao Huang, Zhilu Wang, Shichao Xu, Zhaoran Wang, Qi Zhu 0002. 397-402 [doi]
• LENS: Layer Distribution Enabled Neural Architecture Search in Edge-Cloud HierarchiesMohanad Odema, Nafiul Rashid, Berken Utku Demirel, Mohammad Abdullah Al Faruque. 403-408 [doi]
• AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN InferenceMin Li, Yu Li, Ye Tian, Li Jiang, Qiang Xu. 409-414 [doi]
• An Intelligent Video Processing Architecture for Edge-cloud Video StreamingChengsi Gao, Ying Wang, Weiwei Chen, Lei Zhang. 415-420 [doi]
• PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional TrackingRuoyang Liu, Lu Zhang, Jingyu Wang, Huazhong Yang, Yongpan Liu. 421-426 [doi]
• Obfuscated Priority Assignment to CAN-FD Messages with Dependencies: A Swapping-based and Affix-Matching ApproachGuoqi Xie, Debayan Roy, Yawen Zhang, Renfa Li, Wanli Chang 0001. 427-432 [doi]
• An Efficient Algorithm for Sparse Quantum State PreparationNiels Gleinig, Torsten Hoefler. 433-438 [doi]
• Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit SimulationYuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang. 439-444 [doi]
• Mitigating Crosstalk in Quantum Computers through Commutativity-Based Instruction ReorderingLei Xie, Jidong Zhai, Weimin Zheng. 445-450 [doi]
• QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface CodeYosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi. 451-456 [doi]
• A Bridge-based Compression Algorithm for Topological Quantum CircuitsChen-Hao Hsu, Wan-Hsuan Lin, Wei-Hsiang Tseng, Yao-Wen Chang. 457-462 [doi]
• Quantum Spectral Clustering of Mixed GraphsDaniel Volya, Prabhat Mishra 0001. 463-468 [doi]
• Softermax: Hardware/Software Co-Design of an Efficient Softmax for TransformersJacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan. 469-474 [doi]
• CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded SystemsSalim Ullah, Siva Satyendra Sahoo, Akash Kumar 0001. 475-480 [doi]
• Control Variate Approximation for DNN AcceleratorsGeorgios Zervakis, Ourania Spantidi, Iraklis Anagnostopoulos, Hussam Amrouch, Jörg Henkel. 481-486 [doi]
• BayesFT: Bayesian Optimization for Fault Tolerant Neural Network ArchitectureNanyang Ye, Jingbiao Mei, Zhicheng Fang, Yuwen Zhang, Ziqing Zhang, Huaying Wu, Xiaoyao Liang. 487-492 [doi]
• A Unified DNN Weight Pruning Framework Using Reweighted Optimization MethodsTianyun Zhang, Xiaolong Ma, Zheng Zhan 0001, Shanglin Zhou, Caiwen Ding, Makan Fardad, Yanzhi Wang. 493-498 [doi]
• COSAIM: Counter-based Stochastic-behaving Approximate Integer Multiplier for Deep Neural NetworksShuyuan Yu, Yibo Liu, Sheldon X.-D. Tan. 499-504 [doi]
• Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional ModelingMohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen. 505-510 [doi]
• An Automated and Process-Portable Generator for Phase-Locked LoopZhongkai Wang, Minsoo Choi, Eric Chang, John Wright, Wooham Bae, Sijun Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt 0001, Ayan Biswas, Borivoje Nikolic, Elad Alon. 511-516 [doi]
• Automated Compensation Scheme Design for Operational Amplifier via Bayesian OptimizationJialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng 0001. 517-522 [doi]
• Application of Deep Reinforcement Learning to Dynamic Verification of DRAM DesignsHyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi. 523-528 [doi]
• DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox FuzzingSadullah Canakci, Leila Delshadtehrani, Furkan Eris, Michael Bedford Taylor, Manuel Egele, Ajay Joshi. 529-534 [doi]
• AutoSVA: Democratizing Formal Verification of RTL Module InteractionsMarcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi. 535-540 [doi]
• Theory-Specific Proof Steps Witnessing Correctness of SMT ExecutionsRodrigo Otoni, Martin Blicha, Patrick Eugster, Antti E. J. Hyvärinen, Natasha Sharygina. 541-546 [doi]
• 3D-Adv: Black-Box Adversarial Attacks against Deep Learning Models through 3D SensorsKaichen Yang, Xuan-Yi Lin, Yixin Sun, Tsung-Yi Ho, Yier Jin. 547-552 [doi]
• PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning SystemsAlejandro Hernández-Cano, Rosario Cammarota, Mohsen Imani. 553-558 [doi]
• Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight AttacksSai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo. 559-564 [doi]
• On the Intrinsic Robustness of NVM Crossbars Against Adversarial AttacksDeboleena Roy, Indranil Chakraborty, Timur Ibrayev, Kaushik Roy 0001. 565-570 [doi]
• F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAMBosheng Liu, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen 0003, Yinhe Han, Peng Liu 0045. 571-576 [doi]
• TARe: Task-Adaptive in-situ ReRAM Computing for Graph LearningYintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li. 577-582 [doi]
• PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network AccelerationTao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, Li Jiang. 583-588 [doi]
• RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN AccelerationChen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng. 589-594 [doi]
• Reptail: Cutting Storage Tail Latency with Inherent RedundancyYun-Chih Chen, Chun-Feng Wu, Yuan-Hao Chang 0001, Tei-Wei Kuo. 595-600 [doi]
• MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRankLixiang Li 0003, Yao Chen, Zacharie Zirnheld, Pan Li, Cong Hao. 601-606 [doi]
• Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: An Information-Theoretic ApproachAryan Deshwal, Syrine Belakaria, Ganapati Bhat, Janardhan Rao Doppa, Partha Pratim Pande. 607-612 [doi]
• Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information PropagationXinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha. 613-618 [doi]
• ISA Modeling with Trace Notation for Context Free Property GenerationKeerthikumara Devarajegowda, Endri Kaja, Sebastian Prebeck, Wolfgang Ecker. 619-624 [doi]
• SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous ResetsXingyu Meng, Kshitij Raj, Atul Prasad Deb Nath, Kanad Basu, Sandip Ray. 625-630 [doi]
• Synthesizing Barrier Certificates of Neural Network Controlled Continuous Systems via ApproximationsMeng Sha, Xin Chen, Yuzhe Ji, Qingye Zhao, Zhengfeng Yang, Wang Lin, Enyi Tang, Qiguang Chen, Xuandong Li. 631-636 [doi]
• Approximate Equivalence Checking of Noisy Quantum CircuitsXin Hong, Mingsheng Ying, Yuan Feng 0001, XiangZhen Zhou, Sanjiang Li. 637-642 [doi]
• On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory UsageAntonio Cipolletta, Andrea Calimera. 643-648 [doi]
• Eco-feller: Minimizing the Energy Consumption of Random Forest Algorithm by an Eco-pruning Strategy over MLC NVRAMYu-Pei Liang, Yung-Han Hsu, Tseng-Yi Chen, Shuo-Han Chen, Hsin-Wen Wei, Tsan-sheng Hsu, Wei Kuan Shih. 649-654 [doi]
• Enabling On-Device Self-Supervised Contrastive Learning with Selective Data ContrastYawen Wu, Zhepeng Wang, Dewen Zeng, Yiyu Shi, Jingtong Hu. 655-660 [doi]
• SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMVChenyang Li, Tian Xia, Wenzhe Zhao, Nanning Zheng 0001, Pengju Ren. 661-666 [doi]
• Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic TestingSören Tempel, Vladimir Herdt, Rolf Drechsler. 667-672 [doi]
• Architecture-aware Precision Tuning with Multiple Number Representation SystemsDaniele Cattaneo 0002, Michele Chiari, Nicola Fossati, Stefano Cherubin, Giovanni Agosta. 673-678 [doi]
• PRUID: Practical User Interface Distribution for Multi-surface ComputingMenglong Cui, Mingsong Lv, Qingqiang He, Caiqi Zhang, Chuancai Gu, Tao Yang, Nan Guan. 679-684 [doi]
• A Framework for Optimizing CPU-iGPU Communication on Embedded PlatformsFrancesco Lumpp, Hiren D. Patel, Nicola Bombieri. 685-690 [doi]
• FALCON Down: Breaking FALCON Post-Quantum Signature Scheme through Side-Channel AttacksEmre Karabulut, Aydin Aysu. 691-696 [doi]
• New Predictor-Based Attacks in ProcessorsShuwen Deng, Jakub Szefer. 697-702 [doi]
• Cross-Device Profiled Side-Channel Attacks using Meta-Transfer LearningHonggang Yu, Haoqi Shan, Maximillian Panoff, Yier Jin. 703-708 [doi]
• PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern GenerationTao Zhang, Jungmin Park, Mark Mohammad Tehranipoor, Farimah Farahmandi. 709-714 [doi]
• A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large DesignsZizheng Guo, Tsung-Wei Huang, Yibo Lin. 715-720 [doi]
• GPU-accelerated Path-based Timing AnalysisGuannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong. 721-726 [doi]
• SGL: Spectral Graph Learning from MeasurementsZhuo Feng. 727-732 [doi]
• RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement LearningYi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim. 733-738 [doi]
• A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN AccelerationKyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park 0001. 739-744 [doi]
• ASBP: Automatic Structured Bit-Pruning for RRAM-based NN AcceleratorSongyun Qu, Bing Li, Ying Wang, Lei Zhang. 745-750 [doi]
• ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN TrainingXinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin. 751-756 [doi]
• InstantNet: Automated Generation and Deployment of Instantaneously Switchable-Precision NetworksYonggan Fu, Zhongzhi Yu, Yongan Zhang, Yifan Jiang, Chaojian Li, Yongyuan Liang, Mingchao Jiang, Zhangyang Wang, Yingyan Lin. 757-762 [doi]
• F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar DecodingXiaofan Zhang, Dawei Wang, Pierce Chuang, Shugao Ma, Deming Chen, Yuecheng Li. 763-768 [doi]
• Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack IntegrationHasan Genc, Seah Kim, Alon Amid, Ameer Haj Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert J. Ou, Colin Schmidt 0001, Samuel Steffl, John Wright, Ion Stoica, Jonathan Ragan-Kelley, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao. 769-774 [doi]
• CascadeHD: Efficient Many-Class Learning Framework Using Hyperdimensional ComputingYeseong Kim, Jiseung Kim, Mohsen Imani. 775-780 [doi]
• Cognitive Correlative Encoding for Genome Sequence Matching in Hyperdimensional SystemPrathyush Poduval, Zhuowen Zou, Xunzhao Yin, Elaheh Sadredini, Mohsen Imani. 781-786 [doi]
• Statheros: Compiler for Efficient Low-Precision Probabilistic ProgrammingJacob Laurel, Rem Yang, Atharva Sehgal, Shubham Ugare, Sasa Misailovic. 787-792 [doi]
• TCL: an ANN-to-SNN Conversion with Trainable Clipping LayersNguyen-Dong Ho, Ik Joon Chang. 793-798 [doi]
• Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAsAlberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco D. Santambrogio. 799-804 [doi]
• Exact Neural Networks from Inexact Multipliers via Fibonacci Weight EncodingWilliam Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza. 805-810 [doi]
• PixelSieve: Towards Efficient Activity Analysis From Compressed Video StreamsYongchen Wang, Ying Wang, Huawei Li, Xiaowei Li. 811-816 [doi]
• gGuard: Enabling Leakage-Resilient Memory Isolation in GPU-accelerated Autonomous Embedded SystemsYaswanth Yadlapalli, Husheng Zhou, Yuqun Zhang, Cong Liu 0005. 817-822 [doi]
• PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous VehiclesFeilong Zuo, Zhengxiong Luo, Junze Yu, Zhe Liu, Yu Jiang. 823-828 [doi]
• RoboRun: A Robot Runtime to Exploit Spatial HeterogeneityBehzad Boroujerdian, Radhika Ghosal, Jonathan J. Cruz, Brian Plancher, Vijay Janapa Reddi. 829-834 [doi]
• Neural Pruning Search for Real-Time Object Detection of Autonomous VehiclesPu Zhao, Geng Yuan, Yuxuan Cai, Wei Niu, Qi Liu, Wujie Wen, Bin Ren, Yanzhi Wang, Xue Lin. 835-840 [doi]
• Analyzing and Improving Fault Tolerance of Learning-Based Navigation SystemsZishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury. 841-846 [doi]
• FedLight: Federated Reinforcement Learning for Autonomous Multi-Intersection Traffic Signal ControlYutong Ye, Wupan Zhao, Tongquan Wei, Shiyan Hu, Mingsong Chen. 847-852 [doi]
• PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement LearningRajarshi Roy 0003, Jonathan Raiman, Neel Kant, Ilyas Elkin, Robert Kirby, Michael Y. Siu, Stuart F. Oberman, Saad Godil, Bryan Catanzaro. 853-858 [doi]
• SLAP: A Supervised Learning Approach for Priority Cuts Technology MappingWalter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon. 859-864 [doi]
• TensorLib: A Spatial Accelerator Generation Framework for Tensor AlgebraLiancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang 0001. 865-870 [doi]
• LUT-Based Optimization For ASIC Design FlowLuca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli. 871-876 [doi]
• Deep Integration of Circuit Simulator and SAT SolverHe-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarú, Alan Mishchenko, Robert K. Brayton. 877-882 [doi]
• UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level ModelingShunning Jiang, Yanghui Ou, Peitian Pan, Christopher Batten. 883-888 [doi]
• Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based AcceleratorsChing-Yuan Chen, Krishnendu Chakrabarty. 889-894 [doi]
• Sensitivity Importance Sampling Yield Analysis and Optimization for High Sigma Failure Rate EstimationWenfei Hu, Zhikai Wang, Sen Yin, Zuochang Ye, Yan Wang. 895-900 [doi]
• Reversible Gating Architecture for Rare Failure Detection of Analog and Mixed-Signal CircuitsMyung Seok Shim, Hanbin Hu, Peng Li 0001. 901-906 [doi]
• Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model CalibrationYifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, Bei Yu 0001. 907-912 [doi]
• A New, Computationally Efficient "Blech Criterion" for Immortality in General InterconnectsMohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar. 913-918 [doi]
• EMGraph: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnect Using Graph Convolution NetworksWentian Jin, Liang Chen, Sheriff Sadiqbatcha, Shaoyi Peng, Sheldon X.-D. Tan. 919-924 [doi]
• Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost TradeoffsSai Surya Kiran Pentapati, Sung Kyu Lim. 925-930 [doi]
• Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic InterconnectsYuan Li, Ahmed Louri, Avinash Karanth. 931-936 [doi]
• Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLSXinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, Deming Chen. 937-942 [doi]
• Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA MappingYijiang Guo, Jiarui Wang, Jiaxi Zhang 0001, Guojie Luo. 943-948 [doi]
• CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph AnalyticsSiying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski. 949-954 [doi]
• GNNerator: A Hardware/Software Framework for Accelerating Graph Neural NetworksJacob R. Stevens, Dipankar Das 0002, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan. 955-960 [doi]
• Towards Improving the Trustworthiness of Hardware based Malware Detector using Online Uncertainty EstimationHarshit Kumar, Nikhil Chawla, Saibal Mukhopadhyay. 961-966 [doi]
• On-device Malware Detection using Performance-Aware and Robust Collaborative LearningSanket Shukla, Sai Manoj P. D., Gaurav Kolhe, Setareh Rafatirad. 967-972 [doi]
• SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side ChannelsAndrea Mondelli, Paul Gazzillo, Yan Solihin. 973-978 [doi]
• Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+EvictZili Kou, Wenjian He, Sharad Sinha, Wei Zhang 0012. 979-984 [doi]
• Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based ArchitecturesGhada Dessouky, Mihailo Isakov, Michel A. Kinsy, Pouya Mahmoody, Miguel Mark, Ahmad-Reza Sadeghi, Emmanuel Stapf, Shaza Zeitouni. 985-990 [doi]
• A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer LevelJohannes Müller, Mohammad Rahmani Fadiheh, Anna Lena Duque Antón, Thomas Eisenbarth 0001, Dominik Stoffel, Wolfgang Kunz. 991-996 [doi]
• Helios: Heterogeneity-Aware Federated Learning with Dynamically Balanced CollaborationZirui Xu, Fuxun Yu, Jinjun Xiong, Xiang Chen. 997-1002 [doi]
• Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile DevicesYuhong Song, Weiwen Jiang, Bingbing Li, Panjie Qi, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Sakyasingha Dasgupta, Yiyu Shi, Caiwen Ding. 1003-1008 [doi]
• BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight MatricesZhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun 0003, Guojie Luo. 1009-1014 [doi]
• Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional NetworksMatteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Francesco Conti 0001, Lorenzo Lamberti, Enrico Macii, Luca Benini, Massimo Poncino. 1015-1020 [doi]
• Efficient Tunstall Decoder for Deep Neural Network CompressionChunyun Chen, Zhe Wang, Xiaowei Chen, Jie Lin, Mohamed M. Sabry Aly. 1021-1026 [doi]
• TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance TransferWeixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha. 1027-1032 [doi]
• BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory SystemTao Song, Xiaoming Chen 0003, Xiaoyu Zhang 0002, Yinhe Han. 1033-1038 [doi]
• Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM DevicesHyein Shin, Myeonggu Kang, Lee-Sup Kim. 1039-1044 [doi]
• GRAPHSPY: Fused Program Semantic Embedding through Graph Neural Networks for Memory EfficiencyYixin Guo, Pengcheng Li, Yingwei Luo, Xiaolin Wang 0001, Zhenlin Wang. 1045-1050 [doi]
• NAAS: Neural Accelerator Architecture SearchYujun Lin, Mengtian Yang, Song Han 0003. 1051-1056 [doi]
• SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic EnvironmentsRachmad Vidya Wicaksana Putra, Muhammad Shafique 0001. 1057-1062 [doi]
• High-Performance FPGA-based Accelerator for Bayesian Neural NetworksHongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk. 1063-1068 [doi]
• CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network AcceleratorFebin Sunny, Asif Mirza, Mahdi Nikdast, Sudeep Pasricha. 1069-1074 [doi]
• Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural NetworksThai-Hoang Nguyen, Muhammad Imran 0010, Jaehyuk Choi, Joon-Sung Yang. 1075-1080 [doi]
• Towards Resilient Deployment of In-Memory Neural Networks with High ThroughputBaogang Zhang, Rickard Ewetz. 1081-1086 [doi]
• Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN AcceleratorHanCheon Yun, Hyein Shin, Myeonggu Kang, Lee-Sup Kim. 1087-1092 [doi]
• CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency ImprovementChuxiong Lin, Weifeng He, Yanan Sun 0003, Zhigang Mao, Mingoo Seok. 1093-1098 [doi]
• LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAMYi Wang 0003, Weixuan Chen, Xianhua Wang, Rui Mao 0001. 1099-1104 [doi]
• KV-SSD: What Is It Good For?Manoj Pravakar Saha, Adnan Maruf, Bryan S. Kim, Janki Bhimani. 1105-1110 [doi]
• BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack MemoryChristian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, Jian-Jia Chen. 1111-1116 [doi]
• VLSI Structure-aware Placement for Convolutional Neural Network Accelerator UnitsYun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen. 1117-1122 [doi]
• Ultrafast CPU/GPU Kernels for Density Accumulation in PlacementZizheng Guo, Jing Mai, Yibo Lin. 1123-1128 [doi]
• Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA SystemsMing-Hung Chen, Yao-Wen Chang, Jun-Jie Wang. 1129-1134 [doi]
• REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement LearningJinwei Liu, Gengjie Chen, Evangeline F. Y. Young. 1135-1140 [doi]
• A Complete PCB Routing Methodology with Concurrent Hierarchical RoutingShih-Ting Lin, Hung-Hsiao Wang, Chia-Yu Kuo, Yolo Chen, Yih-Lang Li. 1141-1146 [doi]
• Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular ViasYu-Jie Cai, Yang Hsu, Yao-Wen Chang. 1147-1152 [doi]
• Dynamic Chip Clustering and Task Allocation for Real-time FlashGyeongtaek Kim, Sungjin Lee, Hoon Sung Chwa. 1153-1158 [doi]
• I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time PerformanceZhe Jiang 0004, Kecheng Yang 0001, Yunfeng Ma, Nathan Fisher, Neil C. Audsley, Zheng Dong 0002. 1159-1164 [doi]
• Training Acceleration for Deep Neural Networks: A Hybrid Parallelization StrategyZihao Zeng, Chubo Liu, Zhuo Tang, Wanli Chang 0001, Kenli Li 0001. 1165-1170 [doi]
• Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET ParadigmPaolo Pazzaglia, Daniel Casini, Alessandro Biondi, Marco Di Natale. 1171-1176 [doi]
• A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-LocksZe-Wei Chen, Hang Lei, Maolin Yang, Yong Liao, Lei Qiao. 1177-1182 [doi]
• Designing a 2048-Chiplet, 14336-Core Waferscale ProcessorSaptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar 0002, Puneet Gupta 0001. 1183-1188 [doi]
• Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC OptionsJinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim. 1189-1194 [doi]
• StocHD: Stochastic Hyperdimensional System for Efficient and Robust Learning from Raw DataPrathyush Poduval, Zhuowen Zou, M. Hassan Najafi, Houman Homayoun, Mohsen Imani. 1195-1200 [doi]
• DyGNN: Algorithm and Architecture Support of Dynamic Pruning for Graph Neural NetworksCen Chen, Kenli Li 0001, Xiaofeng Zou, Yangfan Li. 1201-1206 [doi]
• Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAsJinho Lee, Trevor E. Carlson. 1207-1212 [doi]
• MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA VirtualizationYanqiang Liu, Jiacheng Ma, Zhengjun Zhang, Linsheng Li, Zhengwei Qi, Haibing Guan. 1213-1218 [doi]
• DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural NetworksAhmet F. Budak, Prateek Bhansali, Bo Liu 0003, Nan Sun, David Z. Pan, Chandramouli V. Kashyap. 1219-1224 [doi]
• Trust-Region Method with Deep Reinforcement Learning in Analog Design Space ExplorationKai-En Yang, Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang, Feng-Ming Tsai, Chung-An Wang, Yiju Ting, Chia-Shun Yeh, Chin-Tang Lai. 1225-1230 [doi]
• Prioritized Reinforcement Learning for Analog Circuit Optimization With Design KnowledgeN. S. Karthik Somayaji, Hanbin Hu, Peng Li 0001. 1231-1236 [doi]
• Local Bayesian Optimization For Analog Circuit SizingKonstantinos Touloupas, Nikos Chouridis, Paul P. Sotiriadis. 1237-1242 [doi]
• Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural NetworksHao Chen, Keren Zhu 0001, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan. 1243-1248 [doi]
• Interactive Analog Layout Editing with Instant Placement LegalizationXiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin. 1249-1254 [doi]
• SEALing Neural Network Models in Encrypted Deep Learning AcceleratorsPengfei Zuo, Yu Hua 0001, Ling Liang, Xinfeng Xie, Xing Hu 0001, Yuan Xie 0001. 1255-1260 [doi]
• Classifying Computations on Multi-Tenant FPGAsMustafa S. Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, Dustin Richmond. 1261-1266 [doi]
• A Lightweight Isolation Mechanism for Secure Branch PredictorsLutan Zhao, Peinan Li, Rui Hou, Michael C. Huang, Jiazhen Li, Lixin Zhang 0002, Xuehai Qian, Dan Meng. 1267-1272 [doi]
• CuckoOnsai: An Efficient Memory Authentication Using Amalgam of Cuckoo Filters and Integrity TreesOmais Shafi, Ismi Abidi. 1273-1278 [doi]
• Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like MethodJiafeng Xie, Pengzhou He, Wujie Wen. 1279-1284 [doi]
• Optimized Polynomial Multiplier Architectures for Post-Quantum KEM SaberAndrea Basso 0002, Sujoy Sinha Roy. 1285-1290 [doi]
• Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement LearningHaoxing Ren, Matthew Fojtik. 1291-1294 [doi]
• Invited: End-to-End Secure SoC Lifecycle ManagementMd Sami Ul Islam Sami, Fahim Rahman, Farimah Farahmandi, Adam Cron, Mike Borza, Mark Mohammad Tehranipoor. 1295-1298 [doi]
• Invited: Independent Verification and Validation of Security-Aware EDA Tools and IPBenjamin Tan, Siddharth Garg, Ramesh Karri, Yuntao Liu 0001, Michael Zuzak, Abhisek Chakraborty, Ankur Srivastava, Omid Aramoon, Qian Xu, Gang Qu, Adam Porter, Jeno Szep, Warren Savage. 1299-1302 [doi]
• TinyML: Current Progress, Research Challenges, and Future RoadmapMuhammad Shafique 0001, Theocharis Theocharides, Vijay Janapa Reddy, Boris Murmann. 1303-1306 [doi]
• Convergence of SoC architecture and semiconductor manufacturing through AI/ML systemsSrinivas Bodapati, Pushkar Ranade, Ramune Nagisetty. 1307-1310 [doi]
• Safety in Autonomous Driving: Can Tools Offer Guarantees?Daniel J. Fremont, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia. 1311-1314 [doi]
• Requirement Specification, Analysis and Verification for Autonomous SystemsAlessandro Pinto. 1315-1318 [doi]
• Invited: Hardware/Software Co-Synthesis and Co-Optimization for Autonomous SystemsWanli Chang 0001, Shuai Zhao 0004, Simon Burton, Haitong Wang, Ting Chen, Nan Chen, Neil C. Audsley. 1319-1322 [doi]
• Invited: Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and OpportunitiesShaoshan Liu, Bo Yu, Jie Tang 0003, Qi Zhu. 1323-1326 [doi]
• Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex ApplicationsFabrizio Ferrandi, Vito Giovanni Castellana, Serena Curzel, Pietro Fezzardi, Michele Fiorito, Marco Lattuada 0001, Marco Minutoli, Christian Pilato, Antonino Tumeo. 1327-1330 [doi]
• Invited: Getting the Most out of your Circuits with Heterogeneous Logic SynthesisScott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon. 1331-1334 [doi]
• Invited: Accelerating Fully Homomorphic Encryption with Processing in MemorySaransh Gupta, Tajana Simunic Rosing. 1335-1338 [doi]
• Invited: Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast EchocardiographyDewen Zeng, Yukun Ding, Haiyun Yuan, Meiping Huang, Xiaowei Xu 0004, Jian Zhuang, Jingtong Hu, Yiyu Shi. 1339-1342 [doi]
• INVITED: kCC-Net for Compression of Biomedical Image Segmentation NetworksSuraj Mishra, Danny Z. Chen, X. Sharon Hu. 1343-1346 [doi]
• Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution EnvironmentSong Bian 0001, Weiwen Jiang, Takashi Sato. 1347-1350 [doi]
• Building scalable variational circuit training for machine learning tasksKathleen E. Hamilton, Emily Lynn, Tyler Kharazi, Titus Morris, Ryan S. Bennink, Raphael C. Pooser. 1351 [doi]
• Invited: Trainable Discrete Feature Embeddings for Quantum Machine LearningNapat Thumwanit, Chayaphol Lortaraprasert, Rudy Raymond. 1352-1355 [doi]
• Invited: Drug Discovery Approaches using Quantum Machine LearningJunde Li, Mahabubul Alam, Congzhou M. Sha, Jian Wang, Nikolay V. Dokholyan, Swaroop Ghosh. 1356-1359 [doi]
• Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC PlacementAntónio Gusmão, Nuno Horta, Nuno Lourenço 0003, Ricardo Martins 0003. 1360-1361 [doi]
• Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex ConstraintsZhipeng Huang 0009, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, Jianli Chen. 1362-1363 [doi]
• Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask VerificationXiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen. 1364-1365 [doi]
• Late Breaking Results: Incremental 3D Global Routing Considering Cell MovementPeng Zou, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen. 1366-1367 [doi]
• Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph PartitioningJianli Chen, Jiarui Chen, Xiao Shi, Lichong Sun, Jun Yu. 1368-1369 [doi]
• A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical PathsDing-Hao Wang, Pei-Ju Lin, Hui-Ting Yang, Ching-An Hsu, Sin-Han Huang, Mark Po-Hung Lin. 1370-1371 [doi]
• Late Breaking Results: Parallelizing Net Routing with cGANsDmitry Utyamishev, Inna Partin-Vaisband. 1372-1373 [doi]
• Late Breaking Results: Physical Adversarial Attacks of Diffractive Deep Neural NetworksYingjie Li, Cunxi Yu. 1374-1375 [doi]
• Late Breaking Results: Polynomial Formal Verification of Fast AddersAlireza Mahzoon, Rolf Drechsler. 1376-1377 [doi]
• Late Breaking Results: Reinforcement Learning for Scalable Logic Optimization with Graph Neural NetworksXavier Timoneda, Lukas Cavigelli. 1378-1379 [doi]