Table of Contents

• Technology Mapping of Genetic Circuits: From Optimal to Fast SolutionsTobias Schwarz, Christian Hochberger. [doi]
• Reliable Machine Learning for Wearable Activity Monitoring: Novel Algorithms and Theoretical GuaranteesDina Hussein, Taha Belkhouja, Ganapati Bhat, Janardhan Rao Doppa. [doi]
• DaS: Implementing Dense Ising Machines Using Sparse Resistive NetworksNaomi Sagan, Jaijeet Roychowdhury. [doi]
• A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary ConditionsLonglong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng 0001. [doi]
• NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid NetworksHuihong Shi, Haoran You, Yang Zhao 0013, Zhongfeng Wang, Yingyan Lin. [doi]
• Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded NeuronsAyushi Dube, Ankit Wagle, Gian Singh, Sarma B. K. Vrudhula. [doi]
• Garbled EDA: Privacy Preserving Electronic Design AutomationMohammad Hashemi, Steffi Roy, Fatemeh Ganji, Domenic Forte. [doi]
• Attack Directories on ARM big.LITTLE ProcessorsZili Kou, Sharad Sinha, Wenjian He, Wei Zhang. [doi]
• An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0Pei-pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. [doi]
• Hardware Computation Graph for DNN Accelerator Design Automation without Inter-PU TemplatesJun Li, Wei Wang, Wu-Jun Li. [doi]
• Machine Learning for Testing Machine-Learning Hardware: A Virtuous CycleArjun Chaudhuri, Jonti Talukdar, Krishnendu Chakrabarty. [doi]
• Quantum Machine Learning Applications in High-Energy PhysicsAndrea Delgado 0002, Kathleen E. Hamilton. [doi]
• How Good Is Your Verilog RTL Code?: A Quick Answer from Machine LearningPrianka Sengupta, Aakash Tyagi, Yiran Chen 0001, Jiang Hu. [doi]
• Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping ProblemChing-Yao Huang, Chi-Hsiang Lien, Wai-Kei Mak. [doi]
• Re-LSM: A ReRAM-Based Processing-in-Memory Framework for LSM-Based Key-Value StoreQian Wei, Zhaoyan Shen, Yiheng Tong, Zhiping Jia, Lei Ju, Jiezhi Chen, Bingzhe Li. [doi]
• Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic ChipsI-Wei Chiu, Xin-Ping Chen, Jennifer Shueh-Inn Hu, James Chien-Mo Li. [doi]
• A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCSJai-Ming Lin, Po-Chen Lu, Heng-Yu Lin, Jia-Ting Tsai. [doi]
• A Reconfigurable Hardware Library for Robot Scene PerceptionYanqi Liu, Anthony Opipari, Odest Chadwicke Jenkins, R. Iris Bahar. [doi]
• Reliable Computing of ReRAM Based Compute-in-Memory Circuits for AI Edge DevicesMeng-Fan Chang, Je-Ming Hung, Ping-Cheng Chen, Tai-Hao Wen. [doi]
• COSIME: FeFET Based Associative Memory for In-Memory Cosine Similarity SearchChe-Kai Liu, Haobang Chen, Mohsen Imani, Kai Ni 0004, Arman Kazemi, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu, Liang Zhao, Cheng Zhuo, Xunzhao Yin. [doi]
• AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural NetworksTim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch. [doi]
• Inhale: Enabling High-Performance and Energy-Efficient In-SRAM Cryptographic Hash for IoTJingyao Zhang 0002, Elaheh Sadredini. [doi]
• Fault-Tolerant Deep Learning Using RegularizationBiresh Kumar Joardar, Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande. [doi]
• Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer CapabilityYiming Chen, Guodong Yin, Mingyen Lee, Wenjun Tang, Zekun Yang, Yongpan Liu, Huazhong Yang, Xueqing Li. [doi]
• 2fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN AcceleratorsHyein Shin, Myeonggu Kang, Lee-Sup Kim. [doi]
• Towards High Performance and Accurate BNN Inference on FPGA with Structured Fine-Grained PruningKeqi Fu, Zhi Qi, Jiaxuan Cai, Xulong Shi. [doi]
• Personalized Heterogeneity-Aware Federated Search Towards Better Accuracy and Energy EfficiencyZhao Yang, Qingshuang Sun. [doi]
• Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer LearningGuan-Ting Liu, Wei Chen Tai, Yi-Ting Lin, Iris Hui-Ru Jiang, James P. Shiely, Pu-Jen Cheng. [doi]
• SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to SiliconNicolas Bohm Agostini, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Serena Curzel, Fabrizio Ferrandi. [doi]
• QuBRIM: A CMOS Compatible Resistively-Coupled Ising Machine with Quantized Nodal InteractionsYiqiao Zhang, Uday Kumar Reddy Vengalam, Anshujit Sharma, Michael C. Huang 0001, Zeljko Ignjatovic. [doi]
• Squeezing Accumulators in Binary Neural Networks for Extremely Resource-Constrained ApplicationsAzat Azamat, Jaewoo Park, Jongeun Lee. [doi]
• Polynomial Formal Verification: Ensuring Correctness under Resource ConstraintsRolf Drechsler, Alireza Mahzoon. [doi]
• Aging-Aware Training for Printed Neuromorphic CircuitsHaibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. [doi]
• Arjun: An Efficient Independent Support Computation Technique and its Applications to Counting and SamplingMate Soos, Kuldeep S. Meel. [doi]
• 2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical ConnectionsKai-Shun Hu, I-Jye Lin, Yu-Hui Huang, Hao-Yu Chi, Yi Hsuan Wu, Cindy Chin-Fang Shen. [doi]
• Sparse-T: Hardware Accelerator Thread for Unstructured Sparse Data ProcessingPranathi Vasireddy, Krishna Kavi, Gayatri Mehta. [doi]
• DARL: Distributed Reconfigurable Accelerator for Hyperdimensional Reinforcement LearningHanning Chen, Mariam Issa, Yang Ni, Mohsen Imani. [doi]
• A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized LayoutsAlexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl. [doi]
• DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in LithographyQipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang. [doi]
• Romanus: Robust Task Offloading in Modular Multi-Sensor Autonomous Driving SystemsLuke Chen, Mohanad Odema, Mohammad Abdullah Al Faruque. [doi]
• A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation PredictionsRongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam. [doi]
• ObfuNAS: A Neural Architecture Search-Based DNN Obfuscation ApproachTong Zhou, Shaolei Ren, Xiaolin Xu. [doi]
• Workload-Balanced Graph Attention Network Accelerator with Top-K Aggregation CandidatesNaebeom Park, Daehyun Ahn, Jae-Joon Kim. [doi]
• Analyzing and Improving Resilience and Robustness of Autonomous SystemsZishen Wan, Karthik Swaminathan, Pin-Yu Chen, Nandhini Chandramoorthy, Arijit Raychowdhury. [doi]
• ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel ComputationRanyang Zhou, Arman Roohi, Durga Misra, Shaahin Angizi. [doi]
• SHAPE: Scheduling of Fixed-Priority Tasks on Heterogeneous Architectures with Multiple CPUs and Many PEsYuankai Xu, Tiancheng He, Ruiqi Sun, Yehan Ma, Yier Jin, An Zou. [doi]
• False Data Injection Attacks on Sensor SystemsDimitrios Serpanos. [doi]
• On Advancing Physical Design Using Graph Neural NetworksYi-Chen Lu, Sung Kyu Lim. [doi]
• Accelerating N-Bit Operations over TFHE on Commodity CPU-FPGAKevin Nam, Hyunyoung Oh, Hyungon Moon, Yunheung Paek. [doi]
• Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and DataflowRongjian Liang, Jianfeng Song, Yuan Bo, Jiang Hu. [doi]
• ASPPLN: Accelerated Symbolic Probability Propagation in Logic NetworkWeihua Xiao, Weikang Qian. [doi]
• Accelerating Fully Homomorphic Encryption by Bridging Modular and Bit-Level ArithmeticEduardo Chielle, Oleg Mazonka, Homer Gamil, Michail Maniatakos. [doi]
• Sound Source Localization Using Stochastic ComputingPeter Schober, Seyedeh Newsha Estiri, Sercan Aygun, Nima Taherinejad, M. Hassan Najafi. [doi]
• CASU: Compromise Avoidance via Secure Update for Low-End Embedded SystemsIvan De Oliveira Nunes, Sashidhar Jakkamsetti, Youngil Kim, Gene Tsudik. [doi]
• Applying GNNs to Timing Estimation at RTLDaniela Sanchez Lopera, Wolfgang Ecker. [doi]
• EVE: Environmental Adaptive Neural Network Models for Low-Power Energy Harvesting SystemSahidul Islam, Shanglin Zhou, Ran Ran, Yufang Jin, Wujie Wen, Caiwen Ding, Mimi Xie. [doi]
• Qubit Mapping for Reconfigurable Atom ArraysBochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong. [doi]
• A Combined Logical and Physical Attack on Logic ObfuscationMichael Zuzak, Yuntao Liu 0001, Isaac McDaniel, Ankur Srivastava 0001. [doi]
• Overview of 2022 CAD Contest at ICCADYu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato. [doi]
• Temporal Vectorization: A Compiler Approach to Automatic Multi-PumpingCarl-Johannes Johnsen, Tiziano De Matteis, Tal Ben-Nun, Johannes de Fine Licht, Torsten Hoefler. [doi]
• Embracing Graph Neural Networks for Hardware SecurityLilas Alrahis, Satwik Patnaik, Muhammad Shafique 0001, Ozgur Sinanoglu. [doi]
• 2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space ExplorationSicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie 0008. [doi]
• Physics-Aware Differentiable Discrete Codesign for Diffractive Optical Neural NetworksYingjie Li, Ruiyang Chen, Weilu Gao, Cunxi Yu. [doi]
• Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement LearningYan Zhuang, Zhihao Zhang, Dajiang Liu. [doi]
• Fast and Compact Interleaved Modular Multiplication Based on Carry Save AdditionOleg Mazonka, Eduardo Chielle, Deepraj Soni, Michail Maniatakos. [doi]
• ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network AcceleratorsYun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu. [doi]
• FastStamp: Accelerating Neural Steganography and Digital Watermarking of Images on FPGAsShehzeen Hussain, Nojan Sheybani, Paarth Neekhara, Xinqiao Zhang, Javier Duarte, Farinaz Koushanfar. [doi]
• Fine-Granular Computation and Data Layout Reorganization for Improving LocalityMahmut T. Kandemir, Xulong Tang, Jagadish Kotra, Mustafa Karaköy. [doi]
• Robustify ML-Based Lithography Hotspot DetectorsJingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen 0001. [doi]
• Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper)Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen 0059, Mingjie Liu. 1 [doi]
• An MLIR-based Compiler Flow for System-Level Design and Hardware AccelerationNicolas Bohm Agostini, Serena Curzel, Vinay Amatya, Cheng Tan 0002, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, David R. Kaeli, Antonino Tumeo. 6 [doi]
• Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous ArchitectureGokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao 0001. 8 [doi]
• Attacks on Image SensorsMarilyn Wolf, Kruttidipta Samal. 9 [doi]
• Stochastic Mixed-Signal Circuit Design for In-Sensor PrivacyNingyuan Cao, Jianbo Liu, Boyang Cheng, Muya Chang. 11 [doi]
• Sensor Security: Current Progress, Research Challenges, and Future Roadmap (Invited Paper)Anomadarshi Barua, Mohammad Abdullah Al Faruque. 12 [doi]
• SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution ImprovementIsmail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang. 13 [doi]
• HyperEF: Spectral Hypergraph Coarsening by Effective-Resistance ClusteringAli Aghdaei, Zhuo Feng. 14 [doi]
• Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop CellsSoomin Kim, Taewhan Kim. 15 [doi]
• Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package DesignsYang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin. 16 [doi]
• A Mixed Open-Source and Proprietary EDA Commons for Education and PrototypingAndrew B. Kahng. 17 [doi]
• A Scalable Methodology for Agile Chip Development with Open-Source Hardware ComponentsMaico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks 0001, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose. 20 [doi]
• GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex MergingWei Cheng, Chun-Feng Wu, Yuan-Hao Chang 0001, Ing-Chao Lin. 21 [doi]
• Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 ClustersMatheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini. 22 [doi]
• Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA AcceleratorsEdward Richter, Deming Chen. 23 [doi]
• ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer CommunicationEbadollah Taheri, Sudeep Pasricha, Mahdi Nikdast. 24 [doi]
• Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD ToolSwarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava 0001. 25 [doi]
• Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-NetKyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim. 26 [doi]
• A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment InterconnectsOlympia Axelou, Nestor E. Evmorfopoulos, George Floros 0002, George Stamoulis, Sachin S. Sapatnekar. 27 [doi]
• HierPINN-EM: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnects Using Hierarchical Physics-Informed Neural NetworkWentian Jin, Liang Chen, Subed Lamichhane, Mohammadamir Kavousi, Sheldon X.-D. Tan. 28 [doi]
• ScaleHD: Robust Brain-Inspired Hyperdimensional Computing via Adapative ScalingSizhe Zhang, Mohsen Imani, Xun Jiao. 31 [doi]
• Quantitative Verification and Design Space Exploration under Uncertainty with Parametric Stochastic ContractsChanwook Oh, Michele Lora, Pierluigi Nuzzo. 32 [doi]
• Neurally-Inspired Hyperdimensional Classification for Efficient and Robust Biosignal ProcessingYang Ni, Nicholas A. Lesica, Fan-Gang Zeng, Mohsen Imani. 34 [doi]
• Designing Energy-Efficient Decision Tree Memristor Crossbar Circuits Using Binary Classification GraphsPranav Sinha, Sunny Raj. 36 [doi]
• Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural AccelerationHanqing Zhu, Keren Zhu 0001, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne Incorvia, David Z. Pan. 37 [doi]
• GIA: A Reusable General Interposer Architecture for Agile Chiplet IntegrationFuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li. 42 [doi]
• Accelerating Cache Coherence in Manycore Processor through Silicon Photonic ChipletChengeng Li, Fan Jiang, Shixi Chen, Jiaxu Zhang, Yinyi Liu, Yuxiang Fu, Jiang Xu 0001. 43 [doi]
• DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional NetworksYikan Qiu, Yufei Ma 0002, Wentao Zhao, Meng Wu, Le Ye, Ru Huang. 46 [doi]
• Dynamic Frequency Boosting Beyond Critical Path DelayNikolaos Zompakis, Sotirios Xydis. 48 [doi]
• Superfast Full-Scale CPU-Accelerated Global RoutingShiju Lin, Martin D. F. Wong. 51 [doi]
• X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline AlgorithmsZhuolun He, Yuzhe Ma, Bei Yu. 52 [doi]
• GPU-Accelerated Rectilinear Steiner Tree GenerationZizheng Guo, Feng Gu, Yibo Lin. 53 [doi]
• HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis MethodologiesRuifan Xu, Youwei Xiao, Jin Luo, Yun Liang. 54 [doi]
• QCIR: Pattern Matching Based Universal Quantum Circuit Rewriting FrameworkMingyu Chen, Yu Zhang, Yongshang Li, Zhen Wang, Jun Li, Xiangyang Li. 55 [doi]
• Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic SynthesisChang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, Mingxuan Yuan, Jianye Hao. 56 [doi]
• Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing AccelerationXinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng-Ann Heng. 57 [doi]
• AntiSIFA-CAD: A Framework to Thwart SIFA at the Layout LevelRajat Sadhukhan, Sayandeep Saha, Debdeep Mukhopadhyay. 63 [doi]
• Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular StructuresYen-Ting Chen, Yao-Wen Chang. 65 [doi]
• TAG: Learning Circuit Spatial Embedding from LayoutsKeren Zhu 0001, Hao Chen 0059, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren. 66 [doi]
• PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attacks on TouchscreensHuifeng Zhu, Zhiyuan Yu, Weidong Cao, Ning Zhang, Xuan Zhang. 67 [doi]
• Compositional Verification Using a Formal Component and Interface SpecificationYue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik. 72 [doi]
• Usage-Based RTL Subsetting for Hardware AcceleratorsQinhan Tan, Aarti Gupta, Sharad Malik. 73 [doi]
• TransSizer: A Novel Transformer-Based Fast Gate SizerSiddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren. 74 [doi]
• Generation of Mixed-Driving Multi-Bit Flip-Flops for Power OptimizationMeng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang. 75 [doi]
• DEEP: Developing Extremely Efficient Runtime On-Chip Power MetersZhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen 0001, Jiang Hu. 76 [doi]
• Approximate Computing and the Efficient Machine Learning ExpeditionJörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis 0001. 80 [doi]
• HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space ExplorationWilliam Andrew Simon, Una Pale, Tomás Teijeiro, David Atienza. 83 [doi]
• Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi 0001. 87 [doi]
• Language Equation Solving via Boolean Automata ManipulationWan-Hsuan Lin, Chia-Hsuan Su, Jie-Hong R. Jiang. 88 [doi]
• Logic Synthesis for Digital In-Memory ComputingMuhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Rickard Ewetz. 90 [doi]
• Design Space and Memory Technology Co-Exploration for In-Memory Computing Based Machine Learning AcceleratorsKang He, Indranil Chakraborty, Cheng Wang, Kaushik Roy 0001. 91 [doi]
• 2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level CircuitChung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu. 93 [doi]
• IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDAJinwook Jung, Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang. 96 [doi]
• Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper)Yuhui Hao, Bo Yu, Qiang Liu, Shaoshan Liu, Yuhao Zhu 0001. 103 [doi]
• Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper)Lingyi Huang, Xiao Zang, Yu Gong, Bo Yuan 0001. 104 [doi]
• A Robust Quantum Layout Synthesis Algorithm with a Qubit Mapping CheckerTsou-An Wu, Yun-Jhe Jiang, Shao-Yun Fang. 105 [doi]
• MCQA: Multi-Constraint Qubit Allocation for Near-FTQC DeviceSunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang. 108 [doi]
• Smart Scissor: Coupling Spatial Redundancy Reduction and CNN Compression for Embedded HardwareHao Kong, Di Liu 0002, Shuo Huai, Xiangzhong Luo, Weichen Liu, Ravi Subramaniam, Christian Makaya, Qian Lin. 109 [doi]
• On Minimizing the Read Latency of Flash Memory to Preserve Inter-Tree Locality in Random ForestYu-Cheng Lin, Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Shuo-Han Chen, Wei Kuan Shih. 111 [doi]
• Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit SimulationXiaoming Chen 0003. 112 [doi]
• EI-MOR: A Hybrid Exponential Integrator and Model Order Reduction Approach for Transient Power/Ground Network AnalysisCong Wang, Dongen Yang, Quan Chen. 113 [doi]
• Multi-Package Co-Design for Chiplet IntegrationZhen Zhuang, Bei Yu 0001, Kai-Yuan Chao, Tsung-Yi Ho. 114 [doi]
• Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and RedundancyXing Li, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Heng Lu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang. 115 [doi]
• CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer DesignSiyuan Liang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho. 116 [doi]
• Exploiting Uniform Spatial Distribution to Design Efficient Random Number Source for Stochastic ComputingKuncai Zhong, Zexi Li, Haoran Jin, Weikang Qian. 117 [doi]
• Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICsJai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin. 119 [doi]
• Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper)Collin Beaudoin, Satwik Kundu, Rasit Onur Topaloglu, Swaroop Ghosh. 120 [doi]
• AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design PatternsWenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong. 123 [doi]
• LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern ModelingLiangjian Wen, Yi Zhu 0004, Lei Ye, Guojin Chen, Bei Yu, Jianzhuang Liu, Chunjing Xu. 124 [doi]
• WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged LearningQijing Wang, Martin D. F. Wong. 125 [doi]
• Combining BMC and Complementary Approximate Reachability to Accelerate Bug-FindingXiaoyu Zhang, Shengping Xiao, Jianwen Li, Geguang Pu, Ofer Strichman. 126 [doi]
• Equivalence Checking of Dynamic Quantum CircuitsXin Hong, Yuan Feng 0001, Sanjiang Li, Mingsheng Ying. 127 [doi]
• ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell MovementXinshi Zang, Fangzhou Wang, Jinwei Liu, Martin D. F. Wong. 128 [doi]
• A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced ConstraintsZiran Zhu, Fuheng Shen, Yangjie Mei, Zhipeng Huang 0009, Jianli Chen, Jun Yang. 129 [doi]
• Securing Hardware through Reconfigurable Nano-StructuresNima Kavand, Armin Darjani, Shubham Rai, Akash Kumar 0001. 130 [doi]
• Reconfigurable Logic for Hardware IP Protection: Opportunities and ChallengesLuca Collini, Benjamin Tan 0001, Christian Pilato, Ramesh Karri. 131 [doi]
• RT-NeRF: Real-Time On-Device Neural Radiance Fields Towards Immersive AR/VR RenderingChaojian Li, Sixu Li, Yang Zhao 0013, Wenbo Zhu, Yingyan Lin. 132 [doi]
• All-in-One: A Highly Representative DNN Pruning Framework for Edge Devices with Dynamic Power ManagementYifan Gong 0004, Zheng Zhan 0001, Pu Zhao, Yushu Wu, Chao Wu, Caiwen Ding, Weiwen Jiang, Minghai Qin, Yanzhi Wang. 133 [doi]
• Associative Memory Based Experience Replay for Deep Reinforcement LearningMengyuan Li, Arman Kazemi, Ann Franchesca Laguna, X. Sharon Hu. 135 [doi]
• TorchQuantum Case Study for Robust Quantum CircuitsHanrui Wang 0002, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding 0001, Weiwen Jiang, Yiyu Shi 0001, David Z. Pan, Frederic T. Chong, Song Han 0003. 136 [doi]
• DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural NetworksThai-Hoang Nguyen, Muhammad Imran 0010, Joon-Sung Yang. 138 [doi]
• Graph Neural Networks for Idling Error MitigationVedika Servanan, Samah Mohamed Saeed. 139 [doi]
• Quantum Neural Network CompressionZhirui Hu, Peiyan Dong, Zhepeng Wang, Youzuo Lin, Yanzhi Wang, Weiwen Jiang. 140 [doi]
• WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing OptimizationYunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao. 142 [doi]
• Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital ConversionKyeongho Lee, Joonhyung Kim, Jongsun Park 0001. 143 [doi]
• Speculative Load Forwarding Attack on Modern ProcessorsHasini Witharana, Prabhat Mishra 0001. 144 [doi]
• Fast, Robust and Accurate Detection of Cache-Based Spectre Attack PhasesArash Pashrashid, Ali Hajiabadi, Trevor E. Carlson. 145 [doi]
• Combining Gradients and Probabilities for Heterogeneous Approximation of Neural NetworksElias Trommer, Bernd Waschneck, Akash Kumar 0001. 150 [doi]
• Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural NetworksAradhana Mohan Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan. 153 [doi]
• Evaluating the Security of eFPGA-Based Redaction AlgorithmsAmin Rezaei 0001, Raheel Afsharmazayejani, Jordan Maynard. 154 [doi]
• Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware DesignBaleegh Ahmad, Wei-Kai Liu, Luca Collini, Hammond Pearce, Jason M. Fung, Jonathan Valamehr, Mohammad Bidmeshki, Piotr Sapiecha, Steve Brown, Krishnendu Chakrabarty, Ramesh Karri, Benjamin Tan 0001. 157 [doi]
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