Table of Contents

• Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICsAnthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim. [doi]
• 3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal TradeoffsLingjun Zhu, Nesara Eranna Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, Sung Kyu Lim. [doi]
• Identifying Efficient Dataflows for Spiking Neural NetworksDeepika Sharma, Aayush Ankit, Kaushik Roy 0001. [doi]
• A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm NodeJaehoon Jeong, JongHyun Ko, Taigon Song. [doi]
• RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic ComputationZahra Azad, Guowei Yang, Rashmi Agrawal, Daniel Petrisko, Michael B. Taylor, Ajay Joshi. [doi]
• Layerwise Disaggregated Evaluation of Spiking Neural NetworksAbinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan. [doi]
• Drift-tolerant Coding to Enhance the Energy Efficiency of Multi-Level-Cell Phase-Change MemoryYi-Shen Chen, Yuan-Hao Chang 0001, Tei-Wei Kuo. [doi]
• Visible Light Synchronization for Time-Slotted Energy-Aware Transiently-Powered CommunicationAlessandro Torrisi, Maria Doglioni, Kasim Sinan Yildirim, Davide Brunelli. [doi]
• Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout SynthesisSehyeon Chung, Jooyeon Jeong, Taewhan Kim. [doi]
• A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI ApplicationsYigit Tuncel, Anish Krishnakumar, Aishwarya Lekshmi Chithra, Younghyun Kim 0001, Ümit Y. Ogras. [doi]
• Directed Acyclic Graph-based Neural Networks for Tunable Low-Power Computer VisionAbhinav Goel, Caleb Tung, Nick Eliopoulos, Xiao Hu, George K. Thiruvathukal, James C. Davis, Yung-Hsiang Lu. [doi]
• FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose ComputationRanyang Zhou, Arman Roohi, Durga Misra, Shaahin Angizi. [doi]
• Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICsSuwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park. [doi]
• SACS: A Self-Adaptive Checkpointing Strategy for Microkernel-Based Intermittent SystemsYen-Ting Chen, Han-Xiang Liu, Yuan-Hao Chang 0001, Yu-Pei Liang, Wei Kuan Shih. [doi]
• A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT ApplicationsRuicong Chen, H. T. Kung, Anantha P. Chandrakasan, Hae-Seung Lee. [doi]
• A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar DecodingYufan Yue, Tutu Ajayi, Xueyang Liu, Peiwen Xing, Zihan Wang, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim. [doi]
• Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile MemoriesSwati Upadhyay, Arijit Nath, Hemangee Kapoor. [doi]
• Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory EncryptionJingyao Zhang, Hoda Naghibijouybari, Elaheh Sadredini. [doi]
• Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage RegulatorShida Zhang, Nael Mizanur Rahman, Venkata Chaitanya Krishna Chekuri, Carlos Tokunaga, Saibal Mukhopadhyay. [doi]
• Design and Logic Synthesis of a Scalable, Efficient Quantum Number Theoretic TransformChao Lu, Shamik Kundu, Abraham Peedikayil Kuruvila, Supriya Margabandhu Ravichandran, Kanad Basu. [doi]
• Canopy: A CNFET-based Process Variation Aware Systolic DNN AcceleratorCheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen. [doi]
• Predictive Model Attack for Embedded FPGA Logic LockingPrattay Chowdhury, Chaitali Sathe, Benjamin Carrión Schäfer. [doi]
• HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image SensorsTianrui Ma, Weidong Cao, Fei Qiao, Ayan Chakrabarti, Xuan Zhang. [doi]
• A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input ProcessingJoonhyung Kim, Kyeongho Lee, Jongsun Park 0001. [doi]
• Neural Contextual Bandits Based Dynamic Sensor Selection for Low-Power Body-Area NetworksBerken Utku Demirel, Luke Chen, Mohammad Abdullah Al Faruque. [doi]
• Enabling Capsule Networks at the Edge through Approximate Softmax and Squash OperationsAlberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique 0001. [doi]
• QMLP: An Error-Tolerant Nonlinear Quantum MLP Architecture using Parameterized Two-Qubit GatesCheng Chu, Nai-Hui Chia, Lei Jiang, Fan Chen. [doi]
• Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache DevicesYa-Hui Yang, Shuo-Han Chen, Yuan-Hao Chang 0001. [doi]
• Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network AcceleratorsJung Hwan Heo, Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram. [doi]
• Multi-Complexity-Loss DNAS for Energy-Efficient and Memory-Constrained Deep Neural NetworksMatteo Risso, Alessio Burrello, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari. [doi]
• Examining the Robustness of Spiking Neural Networks on Non-ideal Memristive CrossbarsAbhiroop Bhattacharjee, Youngeun Kim, Abhishek Moitra, Priyadarshini Panda. [doi]
• Energy Efficient Cache Design with Piezoelectric FETsReena Elangovan, Ashish Ranjan, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan. [doi]