Abstract is missing.
- Storage Class Memory with Computing Row Buffer: A Design Space ExplorationValentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean Michel Portal. 1-6 [doi]
- From a FPGA Prototyping Platform to a Computing Platform: The MANGO ExperienceJosé Flich, Rafael Tornero, D. Rodriguez, D. Russo, José Maria Martínez, Carles Hernández. 7-12 [doi]
- Heterogeneous Computing Systems for Complex Scientific Discovery WorkflowsChristoph Hagleitner, Dionysios Diamantopoulos, Burkhard Ringlein, Constantinos Evangelinos, Charles R. Johns, Rong N. Chang, Bruce D'Amora, James A. Kahle, James C. Sexton, Michael Johnston, Edward Pyzer-Knapp, Chris Ward. 13-18 [doi]
- Moore's Law and ICT Innovation in the AnthropoceneDavid Bol, Thibault Pirson, Rémi Dekimpe. 19-24 [doi]
- Few hints towards more sustainable AlMarc Duranton. 25 [doi]
- Scalar replacement in the presence of multiple write accesses for high-level synthesisKenshu Seto. 26-31 [doi]
- HOST: HLS Obfuscations against SMT ATtackChandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey, Ramesh Karri. 32-37 [doi]
- Parametric Throughput Oriented Large Integer Multipliers for High Level SynthesisEmanuele Vitali, Davide Gadioli, Fabrizio Ferrandi, Gianluca Palermo. 38-41 [doi]
- Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial EncryptionsZi Wang, Benjamin Carrión Schafer. 42-45 [doi]
- Correlated Multi-objective Multi-fidelity Optimization for HLS Directives DesignQi Sun, Tinghuan Chen, Siting Liu, Jin Miao, Jianli Chen, Hao Yu, Bei Yu 0001. 46-51 [doi]
- Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level SynthesisHannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat. 52-55 [doi]
- OnlineHD: Robust, Efficient, and Single-Pass Online Learning Using Hyperdimensional SystemAlejandro Hernández-Cane, Namiko Matsumoto, Eric Ping, Mohsen Imani. 56-61 [doi]
- Adaptive Generative Modeling in Resource-Constrained EnvironmentsJung-Eun Kim, Richard M. Bradford, Max Del Giudice, Zhong Shao. 62-67 [doi]
- Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime ManagementMatthew Rowlings, Andy M. Tyrrell, Martin A. Trefzer. 68-71 [doi]
- Adaptive Learning Based Building Load Prediction for Microgrid Economic DispatchRumia Masburah, Rajib Lochan Jana, Ainuddin Khan, Shichao Xu, Shuyue Lan, Soumyajit Dey, Qi Zhu 0002. 72-75 [doi]
- Performance Analysis and Auto-tuning for SPARK in-memory analyticsDimitra Nikitopoulou, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris. 76-81 [doi]
- GLAIVE: Graph Learning Assisted Instruction Vulnerability EstimationJiajia Jiao, Debjit Pal, Chenhui Deng, Zhiru Zhang. 82-87 [doi]
- TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments ApplicationsYan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori. 88-93 [doi]
- Forseti: An Efficient Basic-block-level Sensitivity Analysis Framework Towards Multi-bit FaultsJinting Ren, Xianzhang Chen, Duo Liu, Moming Duan, Renping Liu, Chengliang Wang. 94-97 [doi]
- Modeling Silicon-Photonic Neural Networks under UncertaintiesSanmitra Banerjee, Mahdi Nikdast, Krishnendu Chakrabarty. 98-101 [doi]
- Enhancements of Model and Method in Lithography Hotspot IdentificationXuanyu Huang, Rui Zhang, Yu Huang, Peiyao Wang, Mei Li. 102-107 [doi]
- MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization SequencesAlessio Colucci, Dávid Juhász, Martin Mosbeck, Alberto Marchisio, Semeen Rehman, Manfred Kreutzer, Günther Nadbath, Axel Jantsch, Muhammad Shafique 0001. 108-113 [doi]
- Dataflow Restructuring for Active Memory Reduction in Deep Neural NetworksAntonio Cipolletta, Andrea Calimera. 114-119 [doi]
- Efficient Tensor Cores support in TVM for Low-Latency Deep learningWei Sun, Savvas Sioutas, Sander Stuijk, Andrew Nelson 0001, Henk Corporaal. 120-123 [doi]
- Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable ArchitectureYuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng. 124-129 [doi]
- Coyote: An Open Source Simulation Tool to Enable RISC- V in HPCBoria Pérez, Alexander Fell, John D. Davis. 130-135 [doi]
- Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC ProcessorsAdrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes 0001, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji. 136-141 [doi]
- Understanding Chiplets Today to Anticipate Future Integration Opportunities and LimitsGabriel H. Loh, Samuel Naffziger, Kevin Lepak. 142-145 [doi]
- Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design TechnologiesGauthaman Murali, Sung Kyu Lim. 146-151 [doi]
- Advances in Testing and Design-for-Test Solutions for M3D Integrated CircuitsSanmitra Banerjee, Arjun Chaudhuri, Shao-Chun Hung, Krishnendu Chakrabarty. 152-157 [doi]
- 3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures using M3D IntegrationBiresh Kumar Joardar, Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande. 158-163 [doi]
- Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization ProcessKamyar Mohajerani, Richard Haeussler, Rishub Nagpal, Farnoud Farahmand, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj. 164-169 [doi]
- A Deeper Look at the Energy Consumption of Lightweight Block CiphersAndrea Caforio, Fatih Balli, Subhadeep Banik, Francesco Regazzoni 0001. 170-175 [doi]
- Machine Learning Assisted Differential Distinguishers For Lightweight CiphersAnubhab Baksi, Jakub Breier, Yi Chen, Xiaoyang Dong. 176-181 [doi]
- DNFA: Differential No-Fault Analysis of Bit Permutation Based Ciphers Assisted by Side-ChannelXiaolu Hou, Jakub Breier, Shivam Bhasin. 182-187 [doi]
- As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit SimulationStefan Hillmich, Richard Kueng, Igor L. Markov, Robert Wille. 188-193 [doi]
- Stochastic Quantum Circuit Simulation Using Decision DiagramsThomas Grurl, Richard Kueng, Jürgen Fuß, Robert Wille. 194-199 [doi]
- Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX ArchitecturesPhilipp Niemann 0001, Chandan Bandyopadhyay, Rolf Drechsler. 200-205 [doi]
- Automatic Scalable System for the Coverage-Directed Generation (CDG) ProblemRaviv Gal, Eldad Haber, Wesam Ibraheem, Brian Irwin, Ziv Nevo, Avi Ziv. 206-211 [doi]
- Post Silicon Validation of the MMUTom Kolan, Hillel Mendelson, Vitali Sokhin, Shai Doron, Hernan Theiler, Shay Aviv, Hagai Hadad, Natalia Freidman, Elena Tsanko, John M. Ludden, Bryant Cockcroft. 212-217 [doi]
- An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual PrototypesSören Tempel, Vladimir Herdt, Rolf Drechsler. 218-221 [doi]
- A containerized ROS-compliant verification environment for robotic systemsStefano Aldegheri, Nicola Bombieri, Samuele Germiniani, Federico Moschin, Graziano Pravadelli. 222-225 [doi]
- Sim2PIM: A Fast Method for Simulating Host Independent & PIM Agnostic DesignsPaulo C. Santos 0001, Bruno E. Forlin, Luigi Carro. 226-231 [doi]
- COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal SemiperimeterSven Thijssen, Sumit Kumar Jha 0001, Rickard Ewetz. 232-237 [doi]
- SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring ResonatorsJiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan. 238-243 [doi]
- Receptive-Field and Switch-Matrices Based ReRAM Accelerator with Low Digital-Analog Conversion for CNNsYingxun Fu, Xun Liu, Jiwu Shu, Zhirong Shen, Shiye Zhang, Jun Wu, Li Ma. 244-247 [doi]
- An On-chip Layer-wise Training Method for RRAM based Computing-in-memory ChipsYiwen Geng, Bin Gao 0006, Qingtian Zhang, Wenqiang Zhang, Peng Yao, Yue Xi, Yudeng Lin, Junren Chen, Jianshi Tang, Huaqiang Wu, He Qian. 248-251 [doi]
- A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation SensorSarah Azimi, Corrado De Sio, Luca Sterpone. 252-257 [doi]
- Response Time Analysis of Lazy Round RobinYue Tang, Nan Guan, Zhiwei Feng, Xu Jiang 0004, Wang Yi 0001. 258-263 [doi]
- Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's TheoremBehnaz Ranjbar, Ali Hoseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar 0001. 264-269 [doi]
- Virtual Gang Scheduling of Parallel Real-Time TasksWaqar Ali, Rodolfo Pellizzoni, Heechul Yun. 270-275 [doi]
- Future of HPC: Diversifying HeterogeneityDejan S. Milojicic, Paolo Faraboschi, Nicolas Dubé, Duncan Roweth. 276-281 [doi]
- A Data Center Demand Response Policy for Real-World Workload Scenarios in HPCYijia Zhang 0002, Daniel C. Wilson, Ioannis Ch. Paschalidis, Ayse K. Coskun. 282-287 [doi]
- Accelerating data center decarbonization and maximizing renewable usage with grid edge solutionsJohn Glassmire, Hamideh Bitaraf, Stylianos Papadakis, Alexandre Oudalov. 288-293 [doi]
- Distributed Grid computing Manager covering Waste Heat Reuse ConstraintsRémi Bouzel, Yanik Ngoko, Paul Benoit, Nicolas Sainthérant. 294-299 [doi]
- FeFET and NCFET for Future Neural Networks: Visions and OpportunitiesMikail Yayla, Kuan-Hsun Chen, Georgios Zervakis, Jörg Henkel, Jian-Jia Chen, Hussam Amrouch. 300-305 [doi]
- Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning ApplicationsDayane Reis, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu. 306-311 [doi]
- Future Computing Platform Design: A Cross-Layer Design ApproachHsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang 0001, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo. 312-317 [doi]
- Intelligent Architectures for Intelligent Computing SystemsOnur Mutlu. 318-323 [doi]
- Formal Synthesis of Adaptive Droplet Routing for MEDA BiochipsMahmoud Elfar, Tung-Che Liang, Krishnendu Chakrabarty, Miroslav Pajic. 324-329 [doi]
- HyGraph: Accelerating Graph Processing with Hybrid Memory-centric ComputingMinxuan Zhou, Muzhou Li, Mohsen Imani, Tajana Rosing. 330-335 [doi]
- Generic Sample Preparation for Different Microfluidic PlatformsSudip Poddar, Gerold Fink, Werner Haselmayr, Robert Wille. 336-339 [doi]
- RAISE: A Resistive Accelerator for Subject-Independent EEG Signal ClassificationFan Chen, Linghao Song, Hai Helen Li, Yiran Chen. 340-343 [doi]
- Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum ArchitecturesOliver Keszöcze, Naser MohammadZadeh, Robert Wille. 344-349 [doi]
- Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic BiochipsFang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho. 350-353 [doi]
- Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable NanotechnologiesShubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar 0001. 354-359 [doi]
- Autosymmetry of Incompletely Specified FunctionsAnna Bernasconi 0001, Valentina Ciriani. 360-365 [doi]
- Synthesis of SI Circuits from Burst-Mode SpecificationsAlex Chan, Danil Sokolov, Victor Khomenko, David Lloyd, Alex Yakovlev. 366-369 [doi]
- Low-Latency Asynchronous Logic Design for Inference at the EdgeAdrian Wheeldon, Alex Yakovlev, Rishad A. Shafik, Jordan Morris. 370-373 [doi]
- GOMIL: Global Optimization of Multiplier by Integer Linear ProgrammingWeihua Xiao, Weikang Qian, Weiqiang Liu. 374-379 [doi]
- An Event-Driven System-Level Noise Analysis Methodology for RF SystemsChristoph Beyerstedt, Jonas Meier, Fabian Speicher, Ralf Wunderlich, Stefan Heinen. 380-385 [doi]
- OpenSerDes: An Open Source Process-Portable All-Digital Serial LinkK. Gaurav Kumar, Baibhab Chatterjee, Shreyas Sen. 386-391 [doi]
- Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-LineWenhao Wang, Yukui Luo, Xiaolin Xu. 392-395 [doi]
- Digital test of ZigBee transmitters: Validation in industrial test environmentThibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre. 396-401 [doi]
- A Quantization Framework for Neural Network Adaption at the EdgeMengyuan Li, Xiaobo Sharon Hu. 402-407 [doi]
- tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT ApplicationsBehnam Khaleghi, Hanyang Xu, Justin Morris, Tajana Simunic Rosing. 408-413 [doi]
- Resolution-Aware Deep Multi-View Camera SystemsZeinab Hakimi, Vijaykrishnan Narayanan. 414-417 [doi]
- HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture SearchXiangzhong Luo, Di Liu, Shuo Huai, Weichen Liu. 418-421 [doi]
- A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge DevicesZiyi Guan, Shuwei Li, Yuan Cheng, Changhai Man, Wei Mao, Ngai Wong, Hao Yu 0001. 422-427 [doi]
- Enabling and supporting car-as-a-service by digital twin modeling and deploymentCharles Steinmetz, Greyce N. Schroeder, Achim Rettberg, Ricardo N. Rodrigues, Carlos Eduardo Pereira. 428-433 [doi]
- Digital Twin Extension with Extra-Functional PropertiesKhaled Alamin, Sara Vinco, Massimo Poncino, Nicola Dall'Ora, Enrico Fraccaroli, Davide Quaglia. 434-439 [doi]
- Cognitive Digital Twin for Manufacturing SystemsMohammad Abdullah Al Faruque, Deepan Muthirayan, Shih-Yuan Yu, Pramod P. Khargonekar. 440-445 [doi]
- Dynamic fault injection into digital twins of safety-critical systemsThomas Markwirth, Roland Jancke, Christoph Sohrmann. 446-450 [doi]
- Mission Specification and Execution of Multidrone SystemsMarkus Gutmann, Bernhard Rinner. 451-456 [doi]
- Perception Computing-Aware Controller Synthesis for Autonomous SystemsClara Hobbs, Debayan Roy, Parasara Sridhar Duggirala, F. Donelson Smith, Soheil Samii, James H. Anderson, Samarjit Chakraborty. 457-462 [doi]
- Closed-loop Approach to Perception in Autonomous SystemKruttidipta Samal, Marilyn Wolf, Saibal Mukhopadhyay. 463-468 [doi]
- Computing for Control and Control for ComputingXinkai Zhang, Justin M. Bradley. 469-474 [doi]
- QSLC: Quantization-Based, Low-Error Selective Approximation for GPUsSohan Lal, Jan Lucas, Ben H. H. Juurlink. 475-480 [doi]
- Value Similarity Extensions for Approximate Computing in General-Purpose ProcessorsYounghoon Kim, Swagath Venkataramani, Sanchari Sen, Anand Raghunathan. 481-486 [doi]
- TruLook: A Framework for Configurable GPU ApproximationRicardo Garcia, Fatemeh Asgarinejad, Behnam Khaleghi, Tajana Rosing, Mohsen Imani. 487-490 [doi]
- AxPIKE: Instruction-level Injection and Evaluation of Approximate ComputingIsaías B. Felzmann, João Fabrício Filho, Lucas Francisco Wanner. 491-494 [doi]
- A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords RecognitionBo Liu 0019, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai. 495-500 [doi]
- LSP: Collective Cross-Page Prefetching for NVMHaiyang Pan, Yuhang Liu 0001, Tianyue Lu, Mingyu Chen 0001. 501-506 [doi]
- Efficient Hardware-assisted Out-place Update for Persistent MemoryYifu Deng, Jianhui Yue, Zhiyuan Lu, Yifeng Zhu. 507-512 [doi]
- Hardware Acceleration of Fully Quantized BERT for Efficient Natural Language ProcessingZejian Liu, Gang Li 0015, Jian Cheng 0001. 513-516 [doi]
- Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage UnderscalingSeyed Saber Nabavi Larimi, Behzad Salami 0001, Osman S. Unsal, Adrián Cristal Kestelman, Hamid Sarbazi-Azad, Onur Mutlu. 517-522 [doi]
- A GPU -accelerated Deep Stereo- LiDAR Fusion for Real-time High-precision Dense Depth SensingHaitao Meng, Chonghao Zhong, Jianfeng Gu, Gang Chen 0023. 523-528 [doi]
- SPPS: Secure Policy-based Publish/Subscribe System for V2C CommunicationMohammad Hamad, Emanuel Regnath, Jan Lauinger, Vassilis Prevelakis, Sebastian Steinhorst. 529-534 [doi]
- Thermal Comfort Aware Online Energy Management Framework for a Smart Residential BuildingDaichi Watari, Ittetsu Taniguchi, Francky Catthoor, Charalampos Marantos, Kostas Siozios, Elham Shirazi, Dimitrios Soudris, Takao Onoye. 535-538 [doi]
- Online latency monitoring of time-sensitive event chains in safety-critical applicationsJonas Peeck, Johannes Schlatow, Rolf Ernst. 539-542 [doi]
- Intermittent Computing with Efficient State Backup by Asynchronous DMAWei Zhang 0173, Songran Liu, Mingsong Lv, Qiulin Chen, Nan Guan. 543-548 [doi]
- GRINCH: A Cache Attack against GIFT Lightweight CipherCezar Reinbrecht, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil, Johanna Sepúlveda. 549-554 [doi]
- Blind Side-Channel SIFAMelissa Azouaoui, Kostas Papagiannopoulos, Dominik Zürner. 555-560 [doi]
- Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault AttacksAnubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar. 561-564 [doi]
- Side-channel attack on Rainbow post-quantum signatureDavid Pokorný, Petr Socha, Martin Novotný. 565-568 [doi]
- PATRON: A Pragmatic Approach for Encoding Laser Fault Injection Resistant FSMsMuhtadi Choudhury, Domenic Forte, Shahin Tajik. 569-574 [doi]
- An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural NetworksPai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu. 575-580 [doi]
- Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge DevicesWachirawit Ponghiran, Kaushik Roy 0001. 581-586 [doi]
- BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom FilterDehua Liang, Masanori Hashimoto, Hiromitsu Awano. 587-590 [doi]
- Paired Training Framework for Time-Constrained LearningJung-Eun Kim, Richard M. Bradford, Max Del Giudice, Zhong Shao. 591-596 [doi]
- Machine Learning Based Real-Time Industrial Bin-Picking: Hybrid and Deep Learning ApproachesSukhan Lee 0001, Soojin Lee. 597-602 [doi]
- Image analytics and machine learning for in-situ defects detection in Additive ManufacturingDavide Cannizzaro, Antonio Giuseppe Varrella, Stefano Paradiso, Roberta Sampieri, Enrico Macii, Edoardo Patti, Santa Di Cataldo. 603-608 [doi]
- Strengthening Digital Twin Applications based on Machine Learning for Complex EquipmentZijie Ren, Jiafu Wan. 609-614 [doi]
- Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance SpectroscopyFlorian Fricke, Safdar Mahmood, Javier Hoffmann, Marcelo Brandalero, Sascha Liehr, Simon Kern, Klas Meyer, Stefan Kowarik, Stephan Westerdick, Michael Maiwald, Michael Hübner 0001. 615-620 [doi]
- Scramble Cache: An Efficient Cache Architecture for Randomized Set PermutationAmine Jaamoum, Thomas Hiscock, Giorgio Di Natale. 621-626 [doi]
- Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V CoreNils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser. 627-632 [doi]
- Exploring Micro-architectural Side-Channel Leakages through Statistical TestingSarani Bhattacharya, Ingrid Verbauwhede. 633-636 [doi]
- Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory AttacksVishal Gupta 0006, Vinod Ganesan, Biswabandan Panda. 637-640 [doi]
- Tiny-CFA: Minimalistic Control-Flow Attestation Using Verified Proofs of ExecutionIvan De Oliveira Nunes, Sashidhar Jakkamsetti, Gene Tsudik. 641-646 [doi]
- Towards a firmware TPM on RISC-VMarouene Boubakri, Fausto Chiatante, Belhassen Zouari. 647-650 [doi]
- FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic ArraysSurya Selvam, Vinod Ganesan, Pratyush Kumar. 651-656 [doi]
- HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware AcceleratorsRui Xu, Sheng Ma, Yaohua Wang, Yang Guo 0003. 657-662 [doi]
- SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-MatchingSungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim. 663-666 [doi]
- Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNsJingyao Zhang, Huaxi Gu, Grace Li Zhang, Bing Li 0005, Ulf Schlichtmann. 667-672 [doi]
- Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error ToleranceSebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler, Mikail Yayla. 673-678 [doi]
- Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural NetworksCecilia De la Parra, Xuyi Wu, Andre Guntoro, Akash Kumar 0001. 679-684 [doi]
- Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortexDimitrios Stathis 0001, Yu Yang, Ahmed Hemani, Anders Lansner. 685-688 [doi]
- GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural NetworksTianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta. 689-694 [doi]
- A Fairness Conscious Cache Replacement Policy for Last Level CacheKousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das. 695-700 [doi]
- MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency InterconnectMatheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini. 701-706 [doi]
- Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate SimulationQuentin Huppert, Timon Evenblij, Manu Perumkunnil, Francky Catthoor, Lionel Torres, David Novo. 707-710 [doi]
- SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag ArraysRamon Canal, Yiannakis Sazeides, Arkady Bramnik. 711-716 [doi]
- Comparison of GPU Computing Methodologies for Safety-Critical Systems: An Avionics Case StudyMarc Benito, Matina Maria Trompouki, Leonidas Kosmidis, Juan David Garcia, Sergio Carretero, Ken Wenger. 717-718 [doi]
- Verifying the Conformance of a Driver Implementation to the VirtIO SpecificationMatias Vara Larsen. 719-720 [doi]
- Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM TechnologiesYoungbog Yoon, Daeyong Han, Shinho Chu, Sangho Lee, Jaeduk Han, Junhyun Chun. 721-722 [doi]
- HyDREA: Towards More Robust and Efficient Machine Learning Systems with Hyperdimensional ComputingJustin Morris, Kazim Ergun, Behnam Khaleghi, Mohsen Imani, Baris Aksanli, Tajana Rosing. 723-728 [doi]
- DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware ArchitecturesMuhammad Abdullah Hanif, Muhammad Shafique 0001. 729-734 [doi]
- WISER: Deep Neural Network Weight-bit Inversion for State Error Reduction in MLC NAND FlashJaehun Jang, Jong Hwan Ko. 735-738 [doi]
- OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic RedundancyBo Dong, Zheng Wang, Wenxuan Chen, Chao Chen, Yongkui Yang, Zhibin Yu. 739-742 [doi]
- Neuron Fault Tolerance in Spiking Neural NetworksTheofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos. 743-748 [doi]
- Efficient Run-Time Environments for System-Level LET ProgrammingKai-Björn Gemlau, Leonie Köhler, Rolf Ernst. 749-754 [doi]
- Managing Variability and Reuse of Extra-functional Control Software in CPPSBirgit Vogel-Heuser, Juliane Fischer, Dieter Hess, Eva-Maria Neumann, Marcus Würr. 755-760 [doi]
- Quantum computing with CMOS technologyMiguel Fernando Gonzalez-Zalba. 761 [doi]
- Structured Optimized Architecting of Full-Stack Quantum Systems in the NISQ eraCarmen G. Almudéver, Eduard Alarcón. 762-767 [doi]
- Visualizing Decision Diagrams for Quantum Computing (Special Session Summary)Robert Wille, Lukas Burgholzer, Michael Artner. 768-773 [doi]
- Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural ParametersRida El-Allami, Alberto Marchisio, Muhammad Shafique 0001, Ihsen Alouani. 774-779 [doi]
- GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic LockingLilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani Saleh, Muhammad Shafique 0001, Ozgur Sinanoglu. 780-785 [doi]
- Runtime Fault Injection Detection for FPGA-based DNN Execution Using Siamese Path VerificationXianglong Feng, Mengmei Ye, Ke Xia, Sheng Wei 0001. 786-789 [doi]
- RADAR: Run-time Adversarial Weight Attack Detection and Accuracy RecoveryJingtao Li, Adnan Siraj Rakin, Zhezhi He, Deliang Fan, Chaitali Chakrabarti. 790-795 [doi]
- PTierDB: Building Better Read-Write Cost Balanced Key-Value Stores for Small Data on SSDLi Liu, Ke Zhou 0001. 796-801 [doi]
- SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead LoggingQiulin Wu, You Zhou, Fei Wu 0005, Ke Wang, Hao Lv, Jiguang Wan, Changsheng Xie. 802-807 [doi]
- M2H: Optimizing F2FS via Multi-log Delayed Writing and Modified Segment Cleaning based on Dynamically Identified HotnessLihua Yang, Zhipeng Tan, Fang Wang, Shiyun Tu, Jicheng Shao. 808-811 [doi]
- Characterizing and Optimizing EDA Flows for the CloudAbdelrahman Hosny, Sherief Reda. 812-815 [doi]
- Automated Synthesis of Predictable and High-Performance Cache Coherence ProtocolsAnirudh Mohan Kaushik, Hiren D. Patel. 816-821 [doi]
- FPGA Acceleration of Protein Back-Translation and AlignmentSahand Salamat, Jaeyoung Kang 0001, Yeseong Kim, Mohsen Imani, Niema Moshiri, Tajana Rosing. 822-827 [doi]
- FPGA Architectures for Approximate Dense SLAM ComputingMaria Rafaela Gkeka, Alexandros Patras, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas. 828-833 [doi]
- HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA PlatformsHaichang Yang, Zhaoshi Li, Jiawei Wang, Shouyi Yin, Shaojun Wei, Leibo Liu. 834-837 [doi]
- MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGATakashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi. 838-843 [doi]
- LAP: A Lightweight Automata Processor for Pattern Matching TasksHaojun Xia, Lei Gong, Chao Wang, Xianglan Chen, Xuehai Zhou. 844-849 [doi]
- ManiHD: Efficient Hyper-Dimensional Learning Using Manifold Trainable EncoderZhuowen Zou, Yeseong Kim, M. Hassan Najafi, Mohsen Imani. 850-855 [doi]
- Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCsYulhwa Kim, HyungJun Kim, JiHoon Park, Hyunmyung Oh, Jae-Joon Kim. 856-861 [doi]
- A Model-based Design Flow for Asynchronous Implementations from Synchronous SpecificationsYu Bai 0003, Omair Rafique, Klaus Schneider 0001. 862-867 [doi]
- Surviving Transient Power Failures with SRAM Data RetentionSongran Liu, Wei Zhang, Mingsong Lv, Qiulin Chen, Nan Guan. 868-873 [doi]
- RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap AnalysisRobert Balas, Luca Benini. 874-877 [doi]
- Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power MicrocontrollersEmanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva. 878-883 [doi]
- Efficiency-driven Hardware Optimization for Adversarially Robust Neural NetworksAbhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda. 884-889 [doi]
- Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for ScalabilityShamma Nasrin, Priyesh Shukla, Shruthi Jaisimha, Amit Ranjan Trivedi. 890-895 [doi]
- Reliable Edge Intelligence in Unreliable EnvironmentMinah Lee, Xueyuan She, Biswadeep Chakraborty, Saurabh Dash, Burhan Ahmad Mudassar, Saibal Mukhopadhyay. 896-901 [doi]
- Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and PerspectivesNitin Rathi, Amogh Agrawal, Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy 0001. 902-907 [doi]
- A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic ComputingSina Asadi, M. Hassan Najafi, Mohsen Imani. 908-913 [doi]
- Printed Stochastic Computing Neural NetworksDennis D. Weller, Nathaniel Bleier, Michael Hefenbrock, Jasmin Aghassi-Hagmann, Michael Beigl, Rakesh Kumar, Mehdi B. Tahoori. 914-919 [doi]
- Workload-Aware Approximate Computing ConfigurationDongning Ma, Rahul Thapa, Xingjian Wang, Xun Jiao, Cong Hao. 920-925 [doi]
- TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN AcceleratorsGeng Yuan, Payman Behnam, Yuxuan Cai, Ali Shafiee, Jingyan Fu, Zhiheng Liao, Zhengang Li, Xiaolong Ma, Jieren Deng, Jinhui Wang, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding. 926-931 [doi]
- A Runtime Reconfigurable Design of Compute-in-Memory based Hardware AcceleratorAnni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu. 932-937 [doi]
- A Case for Emerging Memories in DNN AcceleratorsAvilash Mukherjee, Kumar Saurav, Prashant Nair, Sudip Shekhar, Mieszko Lis. 938-941 [doi]
- Modeling and Optimization of SRAM-based In-Memory Computing Hardware DesignJyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-sun Seo. 942-947 [doi]
- Fan-out of 2 Triangle Shape Spin Wave Logic GatesAbdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui. 948-953 [doi]
- Towards AQFP-Capable Physical Design AutomationHongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu 0001, Yanzhi Wang, Yibo Lin. 954-959 [doi]
- Implementation of A MEMS Resonator-based Digital to Frequency Converter Using Artificial Neural NetworksXuecui Zou, Sally Ahmed, Hossein Fariborzi. 960-963 [doi]
- Compilation flow for classically defined quantum operationsBruno Schmitt, Ali Javadi-Abhari, Giovanni De Micheli. 964-967 [doi]
- Circuit models for the co-simulation of superconducting quantum computing systemsRohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor. 968-973 [doi]
- Towards Automatic Design and Verification for Level 3 of the European Train Control SystemRobert Wille, Tom Peham, Judith Przigoda, Nils Przigoda. 974-979 [doi]
- Modeling and Analysis for Energy-Driven Computing using Statistical Model-CheckingAbdoulaye Gamatié, Gilles Sassatelli, Marius Mikucionis. 980-985 [doi]
- Blender: A Traffic-Aware Container Placement for Containerized Data CentersZhaorui Wu, Yuhui Deng, Hao Feng, Yi Zhou, Geyong Min. 986-989 [doi]
- SC4MEC: Automated Implementation of A Secure Hierarchical Calculus for Mobile Edge ComputingJiaqi Yin, Huibiao Zhu, Yuan-fei. 990-993 [doi]
- NoC Performance Model for Efficient Network Latency EstimationOumaima Matoussi. 994-999 [doi]
- Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling AttacksTrevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi. 1000-1005 [doi]
- Automated Masking of Software Implementations on Industrial MicrocontrollersArnold Abromeit, Florian Bache, Leon A. Becker, Marc Gourjon, Tim Güneysu, Sabrina Jorn, Amir Moradi 0001, Maximilian Orlt, Falk Schellenberg. 1006-1011 [doi]
- Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAsDennis R. E. Gnad, Vincent Meyers, Nguyen Minh Dang, Falk Schellenberg, Amir Moradi 0001, Mehdi B. Tahoori. 1012-1015 [doi]
- Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry SensingDong-Hyun Seo, Mayukh Nath, Debayan Das, Santosh Ghosh, Shreyas Sen. 1016-1019 [doi]
- A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC SchemeFerhat Yaman, Ahmet Can Mert, Erdinç Öztürk, Erkay Savas. 1020-1025 [doi]
- Logic Synthesis Meets Machine Learning: Trading Exactness for GeneralizationShubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar 0001, Wei Zeng 0015, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee. 1026-1031 [doi]
- Logic Synthesis for Generalization and Learning AdditionYukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita. 1032-1037 [doi]
- ESPRESSO-GPU: Blazingly Fast Two-Level Logic MinimizationHitarth Kanakia, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram. 1038-1043 [doi]
- From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++Bruno Schmitt, Fereshte Mozafari, Giulia Meuli, Heinz Riener, Giovanni De Micheli. 1044-1049 [doi]
- A Resource Estimation and Verification Workflow in Q# Special session paperMathias Soeken, Mariia Mykhailova, Vadym Kliuchnikov, Christopher E. Granade, Alexander Vaschillo. 1050-1055 [doi]
- HiQ-ProjectQ: Towards user-friendly and high-performance quantum computing on GPUsDamien Nguyen, Dmitry Mikushin, Yung Man Hong. 1056-1061 [doi]
- O2NN: Optical Neural Networks with Differential Detection-Enabled Optical OperandsJiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Ray T. Chen, David Z. Pan. 1062-1067 [doi]
- An Efficient Programming Framework for Memristor-based Neuromorphic ComputingGrace Li Zhang, Bing Li 0005, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann. 1068-1073 [doi]
- Efficient Identification of Critical Faults in Memristor Crossbars for Deep Neural NetworksChing-Yuan Chen, Krishnendu Chakrabarty. 1074-1077 [doi]
- Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle VariationZiqi Meng, Weikanu Oian, Yilong Zhao, Yanan Sun, Rui Yang, Li Jiang 0002. 1078-1083 [doi]
- In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable MemoriesArman Kazemi, Mohammad Mehdi Sharifi, Ann Franchesca Laguna, Franz Müller, Ramin Rajaei, Ricardo Olivo, Thomas Kämpfe, Michael T. Niemier, X. Sharon Hu. 1084-1089 [doi]
- Energy-Aware Designs of Ferroelectric Ternary Content Addressable MemoryYu Qian, Zhenhao Fan, Haoran Wang, Chao Li, Mohsen Imani, Kai Ni 0004, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin. 1090-1095 [doi]
- Block Attribute-aware Data Reallocation to Alleviate Read Disturb in SSDsMingwang Zhao, Jun Li 0062, Zhigang Cai, Jianwei Liao, Yuanquan Shi. 1096-1099 [doi]
- Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical RelaysHongtao Zhong, Shengjie Cao, Huazhong Yang, Xueqing Li. 1100-1103 [doi]
- Improving the energy efficiency of STT-MRAM based approximate cacheWei Zhao, Wei Tong, Dan Feng 0001, Jingning Liu, Zhangyu Chen, Jie Xu, Bing Wu, Chengning Wang, Bo Liu. 1104-1109 [doi]
- Verifying Dividers Using Symbolic Computer Algebra and Don't Care OptimizationChristoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler. 1110-1115 [doi]
- ICP and IC3Karsten Scheibler, Felix Winterer, Tobias Seufert, Tino Teige, Christoph Scholl, Bernd Becker 0001. 1116-1121 [doi]
- Optimizing Binary Decision Diagrams for Interpretable Machine Learning ClassificationGianpiero Cabodi, Paolo E. Camurati, Alexey Ignatiev, João Marques-Silva 0001, Marco Palena, Paolo Pasini. 1122-1125 [doi]
- BOFT: Exploitable Buffer Overflow Detection by Information Flow TrackingMuhammad Monir Hossain, Farimah Farahmandi, Mark Mohammad Tehranipoor, Fahim Rahman. 1126-1129 [doi]
- Leveraging Processor Modeling and Verification for General Hardware ModulesYue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik. 1130-1135 [doi]
- Duetto: Latency Guarantees at Minimal Performance CostReza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni. 1136-1141 [doi]
- vProfile: Voltage-Based Anomaly Detection in Controller Area NetworksNathan Liu, Carlos Moreno 0002, Murray Dunne, Sebastian Fischmeister. 1142-1147 [doi]
- Modeling, implementation, and analysis of XRCE-DDS applications in distributed multi-processor real-time embedded systemsSaeid Dehnavi, Dip Goswami, Martijn Koedam, Andrew Nelson 0001, Kees Goossens. 1148-1151 [doi]
- Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCsMaxim Mattheeuws, Björn Forsberg, Andreas Kurth, Luca Benini. 1152-1155 [doi]
- Flexible Cache Partitioning for Multi-Mode Real-Time SystemsOhchul Kwon, Gero Schwäricke, Tomasz Kloda, Denis Hoornaert, Giovani Gracioli, Marco Caccamo. 1156-1161 [doi]
- Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache CoherenceRoger Pujol, Hamid Tabani, Jaume Abella 0001, Mohamed Hassan, Francisco J. Cazorla. 1162-1165 [doi]
- Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking TechniquesNimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu. 1166-1171 [doi]
- A Cognitive SAT to SAT-Hard Clause Translation-based Logic ObfuscationRakibul Hassan, Gaurav Kolhe, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao. 1172-1177 [doi]
- Sequential Logic Encryption Against Model Checking AttackAmin Rezaei, Hai Zhou. 1178-1181 [doi]
- Risk-Aware Cost-Effective Design Methodology for Integrated Circuit LockingYinghua Hu, Kaixin Yang, Subhajit Dutta Chowdhury, Pierluigi Nuzzo. 1182-1185 [doi]
- Hardware Redaction via Designer-Directed Fine-Grained eFPGA InsertionPrashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai. 1186-1191 [doi]
- HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical AbstractionDhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele. 1192-1197 [doi]
- MG-DmDSE: Multi-Granularity Domain Design Space Exploration Considering Function SimilarityJinghan Zhang, Aly Sultan, Hamed Tabkhi, Gunar Schirner. 1198-1203 [doi]
- Formulation of Design Space Exploration Problems by Composable Design Space IdentificationRodolfo Jordão, Ingo Sander, Matthias Becker. 1204-1207 [doi]
- RTL Design Framework for Embedded Processor by using C++ DescriptionEiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki. 1208-1211 [doi]
- An Adaptive Framework for Oversubscription Management in CPU-GPU Unified MemoryDebashis Ganguly, Rami G. Melhem, Jun Yang. 1212-1217 [doi]
- Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout DesignHao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou. 1218-1223 [doi]
- Common-Centroid Layouts for Analog Circuits: Advantages and LimitationsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar. 1224-1229 [doi]
- Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier DesignShengqi Yu, Rishad A. Shafik, Thanasin Bunnam, Kaiyun Chen, Alex Yakovlev. 1230-1233 [doi]
- Analog Layout Generation using Optimized PrimitivesMeghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani. 1234-1239 [doi]
- Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3DFan Chen, Linghao Song, Hai Li, Yiran Chen. 1240-1245 [doi]
- TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D SystemsYenai Ma, Leila Delshadtehrani, Cansu Demirkiran, José L. Abellán, Aiav Joshi. 1246-1251 [doi]
- Thermal-Aware Design and Management of Embedded Real-Time SystemsYoungmoon Lee. 1252-1255 [doi]
- Prediction of Thermal Hazards in a Real Datacenter Room Using Temporal Convolutional NetworksMohsen Seyedkazemi Ardebili, Marcello Zanghieri, Alessio Burrello, Francesco Beneventi, Andrea Acquaviva, Luca Benini, Andrea Bartolini. 1256-1259 [doi]
- Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable DesignYutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto. 1260-1265 [doi]
- Watermarking of Behavioral IPs: A Practical ApproachJianqi Chen, Benjamin Carrión Schafer. 1266-1271 [doi]
- Avrntru: Lightweight NTRU-based Post-Quantum Cryptography for 8-bit AVR MicrocontrollersHao Cheng 0009, Johann Großschädl, Peter B. Rønne, Peter Y. A. Ryan. 1272-1277 [doi]
- SealPK: Sealable Protection Keys for RISC-VLeila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi. 1278-1281 [doi]
- Real-time Private Membership Test using Homomorphic EncryptionEduardo Chielle, Homer Gamil, Michail Maniatakos. 1282-1287 [doi]
- C-PO: A Context-Based Application-Placement Optimization for Autonomous VehiclesTobias Kain, Hans Tompits, Timo Frederik Horeis, Johannes Heinrich, Julian-Steffen Müller, Fabian Plinke, Hendrik Decke, Marcel Aguirre Mehlhorn. 1288-1293 [doi]
- Worst-Case Failover Timing Analysis of Distributed Fail-Operational Automotive ApplicationsPhilipp Weiss, Sherif Elsabbahy, Andreas Weichslgartner, Sebastian Steinhorst. 1294-1299 [doi]
- Decentralized Autonomous Architecture for Resilient Cyber-Physical Production SystemsLaurin Prenzel, Sebastian Steinhorst. 1300-1303 [doi]
- Anomaly Detection and Classification to enable Self-Explainability of Autonomous SystemsFlorian Ziesche, Verena Klös, Sabine Glesner. 1304-1309 [doi]
- Provably-Robust Runtime Monitoring of Neuron Activation PatternsChih-Hong Cheng. 1310-1313 [doi]
- GPU4S: Major Project Outcomes, Lessons Learnt and Way ForwardLeonidas Kosmidis, Iván Rodriguez, Alvaro Jover-Alvarez, Sergi Alcaide, Jérôme Lachaize, Olivier Notebaert, Antoine Certain, David Steenari. 1314-1319 [doi]
- EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platformsChristian Pilato, Stanislav Böhm, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Vojtech Cima, Radim Cmar, Dionysios Diamantopoulos, Fabrizio Ferrandi, Jan Martinovic, Gianluca Palermo, Michele Paolino, Antonio Parodi, Lorenzo Pittaluga, Daniel Raho, Francesco Regazzoni 0001, Katerina Slaninová, Christoph Hagleitner. 1320-1325 [doi]
- Project Overview for Step-Up!CPS - Process, Methods and Technologies for Updating Safety-critical Cyber-physical SystemsThomas Strathmann, Georg Hake, Houssem Guissouma, Carl Philipp Hohl, Yosab Bebawy, Sebastian Vander Maelen, Andrew Koerner. 1326-1329 [doi]
- VeriDevOps: Automated Protection and Prevention to Meet Security Requirements in DevOpsAndrey Sadovykh, Gunnar Widforss, Dragos Truscan, Eduard Paul Enoiu, Wissam Mallouli, Rosa Iglesias, Alessandra Bagnato, Olga Hendel. 1330-1333 [doi]
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- The UP2DATE Baseline Research PlatformsAlvaro Jover-Alvarez, Alejandro J. Calderón, Iván Rodriguez, Leonidas Kosmidis, Kazi Asifuzzaman, Patrick Uven, Kim Grüttner, Tomaso Poggi, Irune Agirre. 1340-1343 [doi]
- MDARTS: Multi-objective Differentiable Neural Architecture SearchSunghoon Kim, Hyun-jeong Kwon, Eunji Kwon, Youngchang Choi, Tae Hyun Oh, Seokhyeong Kang. 1344-1349 [doi]
- Posit Arithmetic for the Training and Deployment of Generative Adversarial NetworksNhut-Minh Ho, Duy Thanh Nguyen, Himeshi De Silva, John L. Gustafson, Weng-Fai Wong, Ik Joon Chang. 1350-1355 [doi]
- Joint Sparsity with Mixed Granularity for Efficient GPU ImplementationChuliang Guo, Xingang Yan, Yufei Chen, He Li, Xunzhao Yin, Cheng Zhuo. 1356-1359 [doi]
- Activation Density based Mixed-Precision Quantization for Energy Efficient Neural NetworksKarina Vasquez, Yeshwanth Venkatesha, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda. 1360-1365 [doi]
- Library-free Structure Recognition for Analog CircuitsMaximilian Neuner, Inga Abel, Helmut Graeb. 1366-1371 [doi]
- Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian OptimizationMingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren. 1372-1377 [doi]
- System Level Verification of Phase-Locked Loop using Metamorphic RelationsMuhammad Hassan 0002, Daniel Große, Rolf Drechsler. 1378-1381 [doi]
- Data-Driven Electrostatics Analysis based on Physics-Constrained Deep learningWentian Jin, Shaoyi Peng, Sheldon X.-D. Tan. 1382-1387 [doi]
- AURORA: Automated Refinement of Coarse-Grained Reconfigurable AcceleratorsCheng Tan, Chenhao Xie 0001, Ang Li, Kevin J. Barker, Antonino Tumeo. 1388-1393 [doi]
- Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA ArchitectureChen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing. 1394-1399 [doi]
- A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM EncodingJainaveen Sundaram, Srivatsa Rangachar Srinivasa, Dileep Kurian, Indranil Chakraborty, Sirisha Rani Kale, Nilesh Jain, Tanay Karnik, Ravi Iyer, Anuradha Srinivasan. 1400-1403 [doi]
- Triple Fixed-Point MAC Unit for Deep LearningMadis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein. 1404-1407 [doi]
- NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural NetworksJungi Lee, Jongeun Lee. 1408-1413 [doi]
- Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor NetworksCyan Subhra Mishra, Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan. 1414-1419 [doi]
- A Deep Learning Approach to Sensor Fusion Inference at the EdgeThomas Becnel, Pierre-Emmanuel Gaillardon. 1420-1425 [doi]
- Neighbor Oblivious Learning (NObLe) for Device Localization and TrackingZichang Liu, Li Chou, Anshumali Shrivastava. 1426-1429 [doi]
- A low-cost BLE-based distance estimation, occupancy detection and counting systemFlorenc Demrozi, Fabio Chiarani, Graziano Pravadelli. 1430-1433 [doi]
- Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular NetworksMeenu Rani Dey, Moumita Patra, Prabhat Mishra 0001. 1434-1439 [doi]
- CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient FaultsHwisoo So, Moslem Didehban, Jinhyo Jung, Aviral Shrivastava, Kyoungwoo Lee. 1440-1445 [doi]
- Estimation of Linux Kernel Execution Path Uncertainty for Safety Software Test CoverageImanol Allende, Nicholas Mc Guire, Jon Pérez 0001, Lisandro Gabriel Monsalve, Javier Fernandez, Roman Obermaisser. 1446-1451 [doi]
- Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating SystemsBenjamin James, Jeffrey Goeders. 1452-1455 [doi]
- Exploring Deep Learning for In-Field Fault Detection in MicroprocessorsSimone Dutto, Alessandro Savino, Stefano Di Carlo. 1456-1459 [doi]
- Reliability-Aware Quantization for Anti-Aging NPUsSami Salamin, Georgios Zervakis, Ourania Spantidi, Iraklis Anagnostopoulos, Jörg Henkel, Hussam Amrouch. 1460-1465 [doi]
- Automated driving safety - The art of conscious risk taking - minimum lateral distances to pedestriansBert Böddeker, Wilhard von Wendorff, Nam Nguyen, Peter Diehl, Roland Meertens, Rolf Johannson. 1466-1471 [doi]
- On safety assurance case for deep learning based image classification in highly automated drivingHimanshu Agarwal, Rafal Dorociak, Achim Rettberg. 1472-1477 [doi]
- Continuous Safety Verification of Neural NetworksChih-Hong Cheng, Rongjie Yan. 1478-1483 [doi]
- HTnet: Transfer Learning for Golden Chip-Free Hardware Trojan DetectionSina Faezi, Rozhin Yasaei, Mohammad Abdullah Al Faruque. 1484-1489 [doi]
- Malicious Routing: Circumventing Bitstream-level Verification for FPGAsQazi Arbab Ahmed, Tobias Wiersema, Marco Platzner. 1490-1495 [doi]
- Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary StudyHonorio Martín, Elena Ioana Vatajelu, Giorgio Di Natale. 1496-1499 [doi]
- Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage CurrentTurki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi 0001. 1500-1503 [doi]
- GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer LevelRozhin Yasaei, Shih-Yuan Yu, Mohammad Abdullah Al Faruque. 1504-1509 [doi]
- Deep Neural Network Hardware Deployment Optimization via Advanced Active LearningQi Sun, Chen Bai, Hao Geng, Bei Yu 0001. 1510-1515 [doi]
- Approach to Improve the Performance Using Bit-level Sparsity in Neural NetworksYesung Kang, Eunji Kwon, Seunggyu Lee, Younghoon Byun, Youngjoo Lee, Seokhyeong Kang. 1516-1521 [doi]
- Morphable Convolutional Neural Network for Biomedical Image SegmentationHuaipan Jiang, Anup Sarma, Mengran Fan, Jihyun Ryoo, Meenakshi Arunachalam, Sharada Naveen, Mahmut T. Kandemir. 1522-1525 [doi]
- Speeding up MUX-FSM based Stochastic Computing for On-device Neural NetworksJongsung Kang, Taewhan Kim. 1526-1529 [doi]
- Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGAShuanglong Liu, Hongxiang Fan, Wayne Luk. 1530-1535 [doi]
- Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent ManagementHisakatsu Yamaguchi, Makiko Ito, Katsuhiro Yoda, Atsushi Ike. 1536-1541 [doi]
- Leveraging Bayesian Optimization to Speed Up Automatic Precision TuningVan-Phu Ha, Olivier Sentieys. 1542-1547 [doi]
- FTApprox: A Fault-Tolerant Approximate Arithmetic Computing Data FormatYe Wang, Jian Dong, Qian Xu, Gang Qu. 1548-1551 [doi]
- Approximate Logic Synthesis of Very Large Boolean NetworksJorge Echavarria, Stefan Wildermann, Jürgen Teich. 1552-1557 [doi]
- Technology Lookup Table based Default Timing Assertions for Hierarchical Timing ClosureRavi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile. 1558-1563 [doi]
- Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock ConstraintsZhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang. 1564-1569 [doi]
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- WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated PipeliningYehuda Kra, Tzachi Noy, Adam Teman. 1574-1579 [doi]
- A Learning-Based Methodology for Accelerating Cell-Aware Model GenerationP. d'Hondt, Aymen Ladhar, Patrick Girard 0001, Arnaud Virazel. 1580-1585 [doi]
- Reliability-Driven Neuromorphic Computing Systems DesignQi Xu, JunPeng Wang, Hao Geng, Song Chen 0001, Xiaoqing Wen. 1586-1591 [doi]
- Testing Resistive Memory based Neuromorphic Architectures using Reference TrimmingChristopher Münch, Mehdi B. Tahoori. 1592-1595 [doi]
- Fault-Criticality Assessment for AI Accelerators using Graph Convolutional NetworksArjun Chaudhuri, Jonti Talukdar, Jinwook Jung, Gi-Joon Nam, Krishnendu Chakrabarty. 1596-1599 [doi]
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- Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed OptimalityWenhong Ma, Guoqi Xie, Renfa Li, Weichen Liu, Hai Helen Li, Wanli Chang 0001. 1899-1904 [doi]
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