Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints - researchr publication

researchr

You are not signed in
Sign in
Sign up

Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang. Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021. pages 1564-1569, IEEE, 2021. [doi]

Abstract is missing.

runs on WebDSL