Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren. Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021. pages 1372-1377, IEEE, 2021. [doi]
Abstract is missing.