Table of Contents

• Flexible architecture of memory BISTsReinaldo Silveira, Qadeer Qureshi, Rodrigo Zeli. 1-6 [doi]
• Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMsG. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen. 1-6 [doi]
• About on-line functionally untestable fault identification in microprocessor cores for safety-critical applicationsRiccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez 0001, Matteo Sonza Reorda. 1-6 [doi]
• Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chainHassen Aziza, Karine Coulié, Wenceslas Rahajandraibe, Remy Vauche. 1-5 [doi]
• Towards evolvable hardware and genetic algorithm operators to fail safe systems achievementGabriel Natan P. Silva, Ricardo O. Duarte. 1-4 [doi]
• Architecture of an industrial analog input designed to meet safety requirementsJoao de Moraes, Taisy Weber, Guilherme Muller, Tiago Dall'Agnol, Rafael Macedo, Elaine P. L. Scartezzini, Roque E. Dapper, Sérgio Cechin, Joao Netto. 1-4 [doi]
• Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenariosPaulo Vinicius Cardoso, Patricia Pitthan Barcelos. 1-6 [doi]
• IJTAG compatible analogue embedded instruments for MPSoC life-time predictionJerrin Pathrose, Ghazanfar Ali, Hans G. Kerkhoff. 1-4 [doi]
• Processor checkpoint recovery for transient faults in critical applicationsPaulo Ricardo Cechelero Villa, Rodrigo Travessini, Fabian Luis Vargas, Eduardo Augusto Bezerra. 1-6 [doi]
• Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologiesAmit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell. 1-5 [doi]
• Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoCFabio Benevenuti, Fernanda Lima Kastensmidt. 1-6 [doi]
• Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injectionGennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio. 1-6 [doi]
• A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRALuiz Carlos Kretly, Ricardo Maltione, Marcelo Gradella Villalva. 1-4 [doi]
• Real-time validation of mixed-criticality applicationsStefano Esposito, Jacopo Sini, Massimo Violante. 1-6 [doi]
• RTOS for mixed criticality applications deployed on NoC-based COTS MPSoCStefano Esposito, Serhiy Avramenko, Massimo Violante. 1-6 [doi]
• A metric-guided gate-sizing methodology for aging guardband reductionAndres F. Gomez, Roberto Gómez, Víctor H. Champac. 1-6 [doi]
• TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specificationsRafael Melo Macieira, Edna Barros. 1-6 [doi]
• Challenges and emerging solutions in testing HBM IO & systemsSalem Abdennadher, Michael Altmann, Bin Xue. 1-4 [doi]
• A fault tolerant dynamically scheduled processor with partial permanent fault handlingFelix Mühlbauer, Lukas Schröder, Mario Schölzel. 1-6 [doi]
• Time domain electrical characterization in zinc oxide nanoparticle thin-film transistorsThales E. Becker, Fábio Fedrizzi Vidor, Gilson I. Wirth, Thorsten Meyers, Julia Reker, Ulrich Hilleringmann. 1-6 [doi]
• A flexible stand-alone FPGA-based ATE for ASIC manufacturing testsDionisio de Carvalho, Bruno Sanches, M. De Carvalho, Wilhelmus A. M. Van Noije. 1-6 [doi]
• Reliability analysis on case-study traffic sign convolutional neural network on APSoCIsrael C. Lopes, Fabio Benevenuti, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Paolo Rech. 1-6 [doi]
• On the use of a failure emulator mechanism at nanosatellite subsystems integration testsCarlos L. G. Batista, Eliane Martins, Maria de Fátima Mattiello-Francisco. 1-6 [doi]
• Direct optimization of a PCI express link equalization in industrial post-silicon validationFrancisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim. 1-6 [doi]
• Fault masking ratio analysis of majority voters topologiesIngrid F. V. Oliveira, Rafael B. Schivittz, Paulo F. Butzen. 1-6 [doi]
• A review of approximate computing techniques towards fault mitigation in HW/SW systemsAlexander Aponte-Moreno, Alejandro Moncada, Felipe Restrepo-Calle, César Pedraza. 1-6 [doi]
• Influence of passive oscillator component variation on OBT sensitivity in OTAsPablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Carlos Vazquez, Tinus Stander, Fortunato C. Dualibe. 1-4 [doi]
• Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module)Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas. 1-4 [doi]
• Analysis of LEON3 systems integration for a Network-on-ChipLucas M. V. Pereira, Douglas R. Melo, Cesar Albenes Zeferino, Eduardo A. Bezerra. 1-3 [doi]
• Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFsWendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee. 1-6 [doi]
• Fault-tolerant architecture with full recovery under presence of SEUAugusto Einsfeldt, Renato Giacomini. 1-4 [doi]
• Defeating hardware Trojan in microprocessor cores through software obfuscationAndrea Marcelli, Ernesto Sánchez 0001, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti, Davide Pola, Alessandro Salvato, Michele Simili. 1-6 [doi]
• Improving approximate-TMR using multi-objective optimization genetic algorithmIuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt. 1-6 [doi]
• Testing approximate digital circuits: Challenges and opportunitiesMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. 1-6 [doi]
• A hardware-based approach for SEU monitoring in SRAMs with weak resistive defectsGeorge Redivo Pinto, Guilherme Cardoso Medeiros, Fabian Vargas, Leticia Bolzani Poehls. 1-6 [doi]
• Probability aware fault-injection approach for SER estimationFábio B. Armelin, Lirida A. B. Naviner, Roberto d'Amore. 1-3 [doi]
• Using FPGA self-produced transients to emulate SETs for SER estimationFábio B. Armelin, Lírida A. B. Naviner, Roberto d'Amore. 1-3 [doi]
• Ionizing radiation modeling in DRAM transistorsMoritz Fieback, Mottaqiallah Taouil, Said Hamdioui, Marco Rovatti. 1-6 [doi]
• Single event effect: Simulations and analysis on 3N163 PMOS transistorJuliano Oliveira, Marcilei Aparecida Guazzelli, Marco Antonio Assis, Renato Giacomini. 1-3 [doi]
• Processor core profiling for SEU effect analysisRodrigo Travessini, Paulo Ricardo Cechelero Villa, Fabian Luis Vargas, Eduardo Augusto Bezerra. 1-6 [doi]
• Error detection method for the ARINC429 communicationMarcos Silveira Santos, Roberto d'Amore. 1-6 [doi]
• Post-silicon validation based on synthetic test patterns for early detection of timing anomaliesEduardo Garcia-Espinosa, Omar Longoria-Gandara, Enrique Gonzalez-Garcia, Arturo Veloz-Guerrero. 1-5 [doi]
• Superimposed in-circuit debugging for self-healing FPGA overlaysAlexandra Kourfali, Dirk Stroobandt. 1-6 [doi]
• Design and test of the RT-NKE task scheduling algorithm for multicore architecturesRenato Severo, Celso Maciel da Costa, Adriane Parraga, Debora Motta, Ivan Muller, Fabian Vargas. 1-6 [doi]
• Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuitsLuis Alberto Contreras Benites, Fernanda Lima Kastensmidt. 1-4 [doi]