Abstract is missing.
- Design and optimisation of NiTi pressure gaugeMartin Hunek, Zdenek Plíva. 1-3 [doi]
- A 50 GHz SiGe BiCMOS active bandpass filterSaurabh Chaturvedi, Mladen Bozanic, Saurabh Sinha. 2-5 [doi]
- An efficient physical design of fully-testable BDD-based circuitsAndreas Rauchenecker, Robert Wille. 6-11 [doi]
- Improving combinational circuit resilience against soft errors via selective resource allocationTohid Taghizad Gogjeh Yaran, Suleyman Tosun. 12-15 [doi]
- Mapping abstract and concrete hardware models for design understandingTino Flenker, Görschwin Fey. 16-21 [doi]
- Mealy-to-moore transformationMustafa Ozgul, Florian Deeg, Sebastian M. Sattler. 22-27 [doi]
- Towards approximation during test of Integrated CircuitsImran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. 28-33 [doi]
- Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed TestMatthias Kampmann, Sybille Hellebrand. 35-41 [doi]
- Fault detection and self repair in Hsiao-code FEC circuitsDavide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus. 42-47 [doi]
- From online fault detection to fault management in Network-on-Chips: A ground-up approachSiavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein. 48-53 [doi]
- Logic testing with test-per-clock pattern loading and improved diagnostic abilitiesOndrej Novák, Zdenek Plíva. 54-59 [doi]
- An analysis of the operation and SET robustness of a CMOS pulse stretching circuitMarko Andjelkovic, Milos Krstic, Rolf Kraemer. 61-66 [doi]
- Analog front-end for precise human body temperature measurementPawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz. 67-72 [doi]
- Body biasing for analog design: Practical experiences in 22 nm FD-SOISunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich. 73-78 [doi]
- A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technologyMichal Wolodzko, Wieslaw Kuzmicz. 79-82 [doi]
- Energy-aware application-specific topology generation for 3D Network-on-ChipsArash Barzinmehr, Suleyman Tosun. 84-87 [doi]
- Firmware Update Manager: A remote firmware reprogramming tool for low-power devicesOndrej Kachman, Marcel Baláz. 88-91 [doi]
- Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generatorMadis Kerner, Kalle Tammemäe. 92-95 [doi]
- Novel metrics for Analog Mixed-Signal coverageAndreas Furtig, Georg Glaeser, Christoph Grimm 0001, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher. 97-102 [doi]
- Cycle-accurate software modeling for RTL verification of embedded systemsMichael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz. 103-108 [doi]
- Structure-preserving modeling of safety-critical combinational circuitsFeim Ridvan Rasim, Canan Kocar, Sebastian M. Sattler. 109-114 [doi]
- Measuring metastability using a time-to-digital converterThomas Polzer, Florian Huemer, Andreas Steininger. 116-121 [doi]
- Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pinsOliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic. 122-126 [doi]
- Ultra-low-voltage driver for large load capacitance in 130nm CMOS technologyMichal Sovcik, Martin Kovác, Daniel Arbet, Viera Stopjaková. 127-132 [doi]
- Are XORs in logic synthesis really necessary?Ivo Halecek, Petr Fiser, Jan Schmidt. 134-139 [doi]
- PMS2UPF: An automated transition from ESL to RTL power-intent specificationMiroslav Siro, Dominik Macko, Katarina Jelemenska. 140-144 [doi]
- Formal Design Space Exploration for memristor-based crossbar architectureMarcello Traiola, Mario Barbareschi, Alberto Bosio. 145-150 [doi]
- A scalable technique to identify true critical paths in sequential circuitsRaimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik. 152-157 [doi]
- On the robustness of memristor based logic gatesLei Xie, Hoang Anh Du Nguyen, Jintao Yu, Mottaqiallah Taouil, Said Hamdioui. 158-163 [doi]
- A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imagingNorbert Druml, Christoph Ehrenhöfer, Walter Bell, Christian Gailer, Hannes Plank, Thomas Herndl, Gerald Holweg. 165-170 [doi]
- A novel architecture for LZSS compression of configuration bitstreams within FPGARadek Isa, Jirí Matousek. 171-176 [doi]
- HLS design of a hardware accelerator for Homomorphic EncryptionAsma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki. 178-183 [doi]
- Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approachesPetr Socha, Vojtech Miskovsky, Hana Kubátová, Martin Novotný. 184-189 [doi]
- Design for three-dimensional sound processor using high-level synthesisSaya Ohira, Tesuya Matsumura. 190-193 [doi]
- Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoCPatrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider. 195-200 [doi]
- On hardware-based fault-handling in dynamically scheduled processorsFelix Mühlbauer, Lukas Schroder, Mario Schölzel. 201-206 [doi]
- Rocket Queue: New data sorting architecture for real-time systemsLukas Kohutka, Viera Stopjaková. 207-212 [doi]