Table of Contents

• Protecting analog circuits with parameter biasing obfuscationVaibhav Venugopal Rao, Ioannis Savidis. 1-6 [doi]
• Fault injection methodology for single event effects on clock-gated ASICsLuis Alberto Contreras Benites, Fernanda Lima Kastensmidt. 1-4 [doi]
• Analysis of routing algorithms generation for irregular NoC topologiesRonaldo Milfont, Paulo Cortez 0002, Alan Cadore Pinheiro, Joao Marcelo Ferreira, Jarbas Silveira, Rafael Mota, César A. M. Marcon. 1-5 [doi]
• Physical-aware pattern selection for stuck-at faultsOscar Acevedo Patino, Juan Carlos Martínez Santos. 1-5 [doi]
• TMR technique for mutex kernel data structuresAlejandro David Velasco, Bartolomeo Montrucchio, Maurizio Rebaudengo. 1-6 [doi]
• MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-ChipsAmir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis. 1-4 [doi]
• Low cost automatic test vector generation for structural analog testingAndre L. Chinazzo, Paulo C. Comassetto de Aguirre, Tiago R. Balen. 1-4 [doi]
• Mixed signal verification to avoid integration mismatch in complex SoCsVinicius Martins, Wang Jiang Chau, Jerson Paulo Guex. 1-6 [doi]
• Identifying high variability speed-limiting paths under agingAnkush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja. 1-6 [doi]
• Post-silicon observability enhancement with topology based trace signal selectionBinod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh. 1-6 [doi]
• Testing multiple stuck-at faults of ROBDD based combinational circuit designToral Shah, Anzhela Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh. 1-6 [doi]
• Practical experience designing and debugging an FPGA for a real-time ethernet industrial busMatheus Berger Oliveira, Joao de Moraes, Sérgio Cechin, Taisy Weber, Joao Netto. 1-6 [doi]
• Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designsM. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco. 1-4 [doi]
• Exploring BDDs to reduce test pattern setGabriel S. Porto, Paulo F. Butzen, Denis Teixeira Franco. 1-4 [doi]
• Contrast of a HDL model and COTS version of a microprocessor for soft-error testingJose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre. 1-6 [doi]
• LFSR characteristic polynomial and phase shifter computation for two-dimensional test set generationOscar Acevedo, Dimitri Kagaris. 1-6 [doi]
• Evaluating the effectiveness of D-chains in SAT-based ATPGJan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker 0001. 1-6 [doi]
• On the detection of board delay faults through the execution of functional programsG. An, Riccardo Cantoro, E. Sanchez, Matteo Sonza Reorda. 1-6 [doi]
• Efficient behavioral intellectual properties source code obfuscation for high-level synthesisNandeesh Veeranna, Benjamin Carrión Schäfer. 1-6 [doi]
• Evaluating the behavior of successive approximation algorithms under soft errorsGennaro Severino Rodrigues, Fernanda Lima Kastensmidt. 1-6 [doi]
• On the development of a high-level fault simulator for the analysis of performance faults on speculative modulesA. Floridia, R. Margelli, E. Sanchez. 1-6 [doi]
• Ionizing radiation effects on a COTS low-cost RISC microcontrollerFelipe G. H. Leite, Roberto B. B. Santos, Nilberto H. Medina, Vitor. A. P. Aguiar, Renato C. Giacomini, Nemitala Added, Fernando Aguirre, Eduardo L. A. Macchione, Fabian Vargas, Marcilei A. G. da Silveira. 1-4 [doi]
• Evaluation of a mixed-signal design diversity system under radiation effectsCarlos J. Gonzalez, Cristiano P. Chenet, Matheus Budelon, Rafael Galhardo Vaz, Odair Lelis Goncalez, Tiago R. Balen. 1-6 [doi]
• Analysis of short defects in FinFET based logic cellsFreddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac. 1-6 [doi]
• SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGAIsrael C. Lopes, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin. 1-6 [doi]
• Evaluation of fault attack detection on SRAM-based FPGAsFabio Benevenuti, Fernanda Lima Kastensmidt. 1-6 [doi]
• Analysis of single-event upsets in a Microsemi ProAsic3E FPGAPaulo R. C. Villa, Roger C. Goerl, Fabian Vargas, Leticia B. Poehls, Nilberto H. Medina, Nemitala Added, Vitor A. P. de Aguiar, Eduardo L. A. Macchione, Fernando Aguirre, Marcilei A. G. da Silveira, Eduardo Augusto Bezerra. 1-4 [doi]
• A DMA and CACHE-based stress schema for burn-in of automotive microcontrollerPaolo Bernardi, Riccardo Cantoro, L. Gianotto, M. Restifo, Ernesto Sánchez, F. Venini, Davide Appello. 1-6 [doi]
• SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-coreThierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco. 1-4 [doi]
• Approximate computing: Design & test for integrated circuitsAlberto Bosio, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi. 1 [doi]
• An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standardEnea Bagalini, J. Sini, Matteo Sonza Reorda, Massimo Violante, H. Klimesch, Peter Sarson. 1-6 [doi]
• Analysis of the implications of stacked devices in nano-scale technologies for analog applicationsIsmael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez. 1-4 [doi]
• An approach to LFSR-based X-masking for built-in self-testSatoshi Ohtake, Daichi Shimazu. 1-4 [doi]
• An effective strategy for selective hardening of softwareFelipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez. 1-6 [doi]
• Handling manufacturing and aging faults with software-based techniques in tiny embedded systemsFelix Mühlbauer, Lukas Schroder, Patryk Skoncej, Mario Schölzel. 1-6 [doi]