Table of Contents

• KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic LockingLevent Aksoy, Muhammad Yasin, Samuel Pagliarini. 1-6 [doi]
• ISPT-Net: A Noval Transient Backward-Stepping Reduction Policy by Irregular Sequential Prediction TransformerYichao Dong, Dan Niu, Zhou Jin 0001, Chuan Zhang 0001, Changyin Sun, Zhenya Zhou. 1-6 [doi]
• A Semi-Tensor Product based Circuit Simulation for SAT-sweepingHongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan Zeng, Zhufei Chu. 1-6 [doi]
• From Designing Quantum Processors to Large-Scale Quantum Computing SystemsCarmen G. Almudéver, Robert Wille, Fabio Sebastiano, Nadia Haider, Eduard Alarcón. 1-10 [doi]
• Formal Methods for High Integrity GPU Software Development and VerificationDimitris Aspetakis, Leonidas Kosmidis, Matina Maria Trompouki, Jose Ruiz, Gábor Marosy. 1-6 [doi]
• Optimizing Imperfectly-Nested Loop Mapping on CGRAs via Polyhedral-Guided FlatteningXingyu Mo, Yawen Li, Dajiang Liu. 1-6 [doi]
• BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural NetworkChi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu. 1-6 [doi]
• Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop ReductionSeungmin Woo, Hyunsoo Lee, Yunjeong Shin, Minseok Han, Yunjeong Go, Jongbeom Kim, Hyundong Lee, Hyunwoo Kim, Taigon Song. 1-6 [doi]
• Circumventing Restrictions in Commercial High-Level Synthesis ToolsBenjamin Carrion Schafer, Chaitali G. Sathe. 1-2 [doi]
• A Compiler Phase to Optimally Split GPU Wavefronts for Safety-Critical SystemsArtem Klashtorny, Mahesh Tripunitara, Hiren D. Patel. 1-6 [doi]
• LoADM: Load-Aware Directory Migration Policy in Distributed File SystemsYuanzhang Wang, Peng Zhang, Fengkui Yang, Ke Zhou, Chunhua Li. 1-6 [doi]
• Hardware-Assisted Control-Flow Integrity Enhancement for IoT DevicesWeiyi Wang, Lang Feng, Zhiguo Shi, Cheng Zhuo, Jiming Chen 0001. 1-6 [doi]
• PhotonNTT: Energy-Efficient Parallel Photonic Number Theoretic Transform AcceleratorXianbin Li, Jiaqi Liu, Yuying Zhang, Yinyi Liu, Jiaxu Zhang, Chengeng Li, Shixi Chen, Yuxiang Fu, Fengshi Tian, Wei Zhang, Jiang Xu. 1-6 [doi]
• Towards Efficient Reconfiguration through Lightweight Input Inversion for MLC NVFPGAsHuichuan Zheng, Mengying Zhao, Hao Zhang, Yuqing Xiong, Xiaojun Cai, Zhiping Jia. 1-6 [doi]
• AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model PredictionZhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang. 1-2 [doi]
• Alleviating Barren Plateaus in Parameterized Quantum Machine Learning Circuits: Investigating Advanced Parameter Initialization StrategiesMuhammad Kashif, Muhammad Rashid, Saif Al-Kuwari, Muhammad Akmal Shafique. 1-6 [doi]
• Class-Aware Pruning for Efficient Neural NetworksMengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang. 1-6 [doi]
• Optimal Fixed Priority Scheduling in Multi-Stage Multi-Resource Distributed Real-Time SystemsNiraj Kumar, Chuanchao Gao, Arvind Easwaran. 1-6 [doi]
• CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural NetworksKavitha S, Binsu J. Kailath, Bhupendra Singh Reniwal. 1-2 [doi]
• Orchestration-Aware Optimization of ROS2 Communication ProtocolsMirco De Marchi, Nicola Bombieri. 1-6 [doi]
• Driving Autonomy with Event-Based Cameras: Algorithm and Hardware PerspectivesNael Mizanur Rahman, Uday Kamal, Manish Nagaraj, Shaunak Roy, Saibal Mukhopadhyay. 1-6 [doi]
• NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AISoyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori. 1-6 [doi]
• Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power ComputingSatoshi Kawakami, Yusuke Ohtusbo, Koji Inoue, Masamitsu Tanaka. 1-2 [doi]
• MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware RetargetingPierpaolo Morì, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone. 1-6 [doi]
• Cache Bandwidth Contention Leaks SecretsHan Wang, Ming Tang 0002, Ke Xu, Quancheng Wang. 1-6 [doi]
• An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation ConstraintLingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu. 1-6 [doi]
• CycPUF: Cyclic Physical Unclonable FunctionMichael Dominguez, Amin Rezaei. 1-6 [doi]
• Adaptive Localization for Autonomous Racing Vehicles with Resource-Constrained Embedded PlatformsFederico Gavioli, Gianluca Brilli, Paolo Burgio, Davide Bertozzi. 1-6 [doi]
• Communication-Efficient Model Parallelism for Distributed In-Situ Transformer InferenceYuanxin Wei, Shengyuan Ye, Jiazhi Jiang, Xu Chen, Dan Huang, Jiangsu Du, Yutong Lu. 1-6 [doi]
• A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN ApplicationKuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang. 1-6 [doi]
• A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel TracesGiuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni. 1-6 [doi]
• AMBEATion: Analog Mixed-Signal Back-End Design Automation with Machine Learning and Artificial Intelligence TechniquesGiulia Elena Aliffi, Joao Baixinho, Dalibor Barri, Francesco Daghero, Nicola Di Carolo, Gabriele Faraone, Michelangelo Grosso, Daniele Jahier Pagliari, Jiri Jakovenko, Vladimír Janícek, Dario Licastro, Vazgen Melikyan, Matteo Risso, Vittorio Romano, Eugenio Serianni, Martin Stastný, Patrik Vacula, Giorgia Vitanza, Chen Xie. 1-6 [doi]
• Security Layers and Related Services within the Horizon Europe NEUROPULS ProjectFabio Pavanello, Cédric Marchand 0002, Paul Jiménez, Xavier Letartre, Ricardo Chaves, Niccolò Marastoni, Alberto Lovato, Mariano Ceccato, George Papadimitriou 0001, Vasileios Karakostas, Dimitris Gizopoulos, Roberta Bardini, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino, Laurence Lerch, Ulrich Rührmair, Sergio Vinagrero Gutierrez, Giorgio Di Natale, Elena Ioana Vatajelu. 1-6 [doi]
• Towards an Embedded System for Failure Diagnosis in Drones Using AI and SAC-DM on FPGARafael Batista, Matthias Nickel, Alexander Lehnert, Sergio A. Pertuz 0001, Marc Reichenbach, Diana Goehringer, Alisson Brito. 1-2 [doi]
• On-Sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-DesignGiorgos Armeniakos, Paula L. Duarte, Priyanjana Pal, Georgios Zervakis 0001, Mehdi B. Tahoori, Dimitrios Soudris. 1-6 [doi]
• DIAPASON: Differentiable Allocation, Partitioning and Fusion of Neural Networks for Distributed InferenceFederico Nicolás Peccia, Alexander Viehl, Oliver Bringmann 0001. 1-6 [doi]
• RLPlanner: Reinforcement Learning Based Floorplanning for Chiplets with Fast Thermal AnalysisYuanyuan Duan, Xingchen Liu, Zhiping Yu, HanMing Wu, Leilai Shao, Xiaolei Zhu. 1-2 [doi]
• An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU ArchitectureJiahang Lou, Xuchen Gao, Yiqing Mao, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang. 1-6 [doi]
• SGPRS: Seamless GPU Partitioning Real-Time Scheduler for Periodic Deep Learning WorkloadsAmir Fakhim-Babaei, Thidapat Chantem. 1-2 [doi]
• BESWAC: Boosting Exact Synthesis via Wiser SAT Solver CallSunan Zou, Jiaxi Zhang 0001, Bizhao Shi, Guojie Luo. 1-6 [doi]
• KIHT: Kaligo-Based Intelligent Handwriting TeacherTanja Harbaum, Alexey Serdyuk, Fabian Kreß, Tim Hamann, Jens Barth, Peter Kämpf, Florent Imbert, Yann Soullard, Romain Tavenard, Éric Anquetil, Jessica Delahaie. 1-6 [doi]
• Autonomous Realization of Safety- and Time-Critical Embedded Artificial IntelligenceJoakim Lindén, Andreas Ermedahl, Hans Salomonsson, Masoud Daneshtalab, Björn Forsberg, Paris Carbone. 1-4 [doi]
• OC-DLRM: Minimizing the I/O Traffic of DLRM Between Main Memory and OCSSDShang-Hung Ti, Tseng-Yi Chen, Tsung Tai Yeh, Shuo-Han Chen, Yu-Pei Liang. 1-2 [doi]
• A DTCO Framework for 3D NAND Flash ReadoutMattia Gerardi, Arvind Sharma, Yang Xiang, Jakub Kaczmarek, Fernando García-Redondo, Maarten Rosmeulen, Marie Garcia Bardon. 1-2 [doi]
• An Efficient Logic Operation Scheduler for Minimizing Memory Footprint of In-Memory SIMD ComputationXingyue Qian, Zhezhi He, Weikang Qian. 1-2 [doi]
• Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient DescentSosei Ikeda, Hiromitsu Awano, Takashi Sato. 1-6 [doi]
• AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive PositJingyu He, Fengbin Tu, Kwang-Ting Cheng, Chi-Ying Tsui. 1-2 [doi]
• ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic AnalysisTsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng. 1-2 [doi]
• Shared Data Kills Real-Time Cache Analysis. How to Resurrect It?Safin Bayes, Mohamed Hossam, Mohamed Hassan 0002. 1-6 [doi]
• From Master Equation to SPICE: A Platform to Model Cryo-CMOS Control for QubitsVladimir Pesic, Andrew Wright, Edoardo Charbon. 1-6 [doi]
• High-Efficiency FPGA - Based Approximate Multipliers with LUT Sharing and Carry SwitchingYi Guo, Qilin Zhou, Xiu Chen, Heming Sun. 1-2 [doi]
• Formal Verification of Secure Boot ProcessSriram Vasudevan, Prasanna Ravi, Arpan Jati, Shivam Bhasin, Anupam Chattopadhyay. 1-6 [doi]
• FMTT: Fused Multi-Head Transformer with Tensor-Compression for 3D Point Clouds Detection on Edge DevicesZikun Wei, Tingting Wang, Chenchen Ding, Bohan Wang, Ziyi Guan, Hantao Huang, Hao Yu 0001. 1-6 [doi]
• CRISP: Hybrid Structured Sparsity for Class-Aware Model PruningShivam Aggarwal, Kuluhan Binici, Tulika Mitra. 1-6 [doi]
• SEAL: Sensing Efficient Active Learning on Wearables through Context-awarenessHamidreza Alikhani, Ziyu Wang, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani, Nikil D. Dutt. 1-2 [doi]
• Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian ProcessYuta Shintani, Michiko Inoue, Michihiro Shintani. 1-6 [doi]
• Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZoneYun Chen, Arash Pashrashid, Yongzheng Wu, Trevor E. Carlson. 1-6 [doi]
• CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement LearningSung Yun Lee, Kyungjun Min, Seokhyeong Kang. 1-6 [doi]
• A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST ApproachChristian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillon, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva 0002, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni 0001, Burkhard Ringlein, Roberto Rocco, Katerina Slaninová, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner. 1-6 [doi]
• Optimizing Offload Performance in Heterogeneous MPSoCsLuca Colagrande, Luca Benini. 1-2 [doi]
• Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference AcceleratorsLixia Han, Peng Huang 0004, Zheng Zhou, Yiyang Chen, Haozhang Yang, Xiaoyan Liu, JinFeng Kang. 1-2 [doi]
• PP-HDC: A Privacy-Preserving Inference Framework for Hyperdimensional ComputingRuixuan Wang, Wengying Wen, Kyle Juretus, Xun Jiao. 1-6 [doi]
• ObfusGate: Representation Learning-Based Gatekeeper for Hardware-Level Obfuscated Malware DetectionZhangying He, Chelsea William Fernandes, Hossein Sayadi. 1-2 [doi]
• Search-in-Memory (SiM): Conducting Data-Bound Computations on Flash Chip for Enhanced EfficiencyYun-Chih Chen, Yuan-Hao Chang 0001, Tei-Wei Kuo. 1-2 [doi]
• A Novel March Test Algorithm for Testing 8T SRAM-Based IMC ArchitecturesLila Ammoura, Marie-Lise Flottes, Patrick Girard 0001, Jean-Philippe Noel, Arnaud Virazel. 1-6 [doi]
• Towards Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H -Si $(100)-2\times 1$ SurfaceMarcel Walter, Jeremiah Croshaw, Samuel Sze Hang Ng, Konrad Walus, Robert A. Wolkow, Robert Wille. 1-2 [doi]
• Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error AnalysisZdenek Vasícek, Vojtech Mrazek, Lukás Sekanina. 1-6 [doi]
• CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory ArchitecturesRebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph. 1-6 [doi]
• A Deep-Learning-Based Statistical Timing Prediction Method for Sub-16nm TechnologiesJiajie Xu, Leilei Jin, Wenjie Fu, Longxing Shi. 1-6 [doi]
• Complete and Efficient Verification for a RISC-V Processor Using Formal VerificationLennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler. 1-6 [doi]
• Scalable Sequential Optimization Under Observability Don't CaresDewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù. 1-6 [doi]
• Data Center Demand Response for Sustainable Computing: Myth or Opportunity?Ayse K. Coskun, Fatih Acun, Quentin Clark, Can Hankendi, Daniel Curtis Wilson. 1-2 [doi]
• EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to EdgePatrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker 0001, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer. 1-6 [doi]
• Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro PlacementXiaotian Zhao, Tianju Wang, Run Jiao, Xinfei Guo. 1-6 [doi]
• An Endeavor to Industrialize Hardware Fuzzing: Automating NoC Verification in UVMRuiyang Ma, Huatao Zhao, Jiayi Huang, Shijian Zhang, Guojie Luo. 1-2 [doi]
• IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge SecurityHanyong Shao, Boyi Fu, Jinghao Yang, Wenpu Luo, Chang Su, Zhiyuan Fu, Kechao Tang, Ru Huang. 1-6 [doi]
• ROLDEF: RObust Layered DEFense for Intrusion Detection Against Adversarial AttacksOnat Güngör, Tajana Rosing, Baris Aksanli. 1-6 [doi]
• OTFGEncoder - HDC: Hardware-efficient Encoding Techniques for Hyperdimensional ComputingMahboobe Sadeghipour Roodsari, Jonas Krautter, Mehdi B. Tahoori. 1-2 [doi]
• STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML WorkloadsEdward Manca, Luca Urbinati, Mario R. Casu. 1-6 [doi]
• Bitstream Fault Injection Attacks on CRYSTALS Kyber Implementations on FPGAsZiying Ni, Ayesha Khalid, Weiqiang Liu 0001, Máire O'Neill. 1-6 [doi]
• Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUFShengjie Zhou, Yongliang Chen, Xiaole Cui, Yun Liu. 1-6 [doi]
• ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT AccelerationZhenyu Guan, Yongqing Zhu, Yicheng Huang, Luchang Lei, Xueyan Wang, Hongyang Jia, Yi Chen, Bo Zhang, Jin Dong, Song Bian 0001. 1-6 [doi]
• Constraint-Aware Resource Management for Cyber-Physical SystemsJustin McGowen, Ismet Dagli, Neil T. Dantam, Mehmet E. Belviranli. 1-2 [doi]
• DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware AcceleratorsTom Glint, Mithil Pechimuthu, Joycee Mekie. 1-6 [doi]
• Learning to Floorplan like Human Experts via Reinforcement LearningBinjie Yan, Lin Xu, Zefang Yu, Mingye Xie, Wei Ran, Jingsheng Gao, Yuzhuo Fu, Ting Liu. 1-2 [doi]
• XiNet-pose: Extremely Lightweight Pose Detection for MicrocontrollersAlberto Ancilotto, Francesco Paissan, Elisabetta Farella. 1-6 [doi]
• Auto WS: Automate Weights Streaming in Layer-Wise Pipelined DNN AcceleratorsZhewen Yu, Christos-Savvas Bouganis. 1-6 [doi]
• Certainty or Intelligence: Pick One!Edward A. Lee. 1-2 [doi]
• BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0Emad Malekzadeh Arasteh, Vivek Govindasamy, Rainer Dömer. 1-6 [doi]
• Adaptive Deep Learning for Efficient Visual Pose Estimation Aboard Ultra-Low-Power Nano-DronesBeatrice Alessandra Motetti, Luca Crupi, Mustafa Omer Mohammed Elamin Elshaigi, Matteo Risso, Daniele Jahier Pagliari, Daniele Palossi, Alessio Burrello. 1-6 [doi]
• PIMSYN: Synthesizing Processing-in-Memory CNN AcceleratorsWanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han 0001, Xiaoming Chen 0003. 1-6 [doi]
• MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC AnalysisZhou Jin 0001, Tian Feng, Xiao Wu, Dan Niu, Zhenya Zhou, Cheng Zhuo. 1-6 [doi]
• ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision TransformerTong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang 0001. 1-6 [doi]
• A Modular Branch Predictor Performance Analysis Framework for Fast Design Space ExplorationYa Wang, Hanwei Fan, Sicheng Li, Tingyuan Liang, Wei Zhang. 1-6 [doi]
• RTSA: An RRAM-TCAM based In-Memory-Search Accelerator for Sub-100 µs Collision DetectionJiahao Sun, Fangxin Liu, Yijian Zhang, Li Jiang, Rui Yang. 1-2 [doi]
• Multi-Level Analysis of GPU Utilization in ML Training WorkloadsPaul Delestrac, Debjyoti Bhattacharjee, Simei Yang, Diksha Moolchandani, Francky Catthoor, Lionel Torres, David Novo. 1-6 [doi]
• uHD: Unary Processing for Lightweight and Dynamic Hyperdimensional ComputingSercan Aygun, Mehran Shoushtari Moghadam, M. Hassan Najafi. 1-6 [doi]
• A Concealable RRAM Physical Unclonable Function Compatible with In-Memory ComputingJiang Li, Yijun Cui, Chenghua Wang, Weiqiang Liu 0001, Shahar Kvatinsky. 1-6 [doi]
• Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning ReasonerBo Yang, Qi Xu, Hao Geng, Song Chen, Yi Kang. 1-6 [doi]
• Dynamic Reconfigurable Security Cells Based on Emerging Devices Integrable in FDSOI TechnologyNiladri Bhattacharjee, Viktor Havel, Suruchi Kumari, Nima Kavand, Jorge Navarro Quijada, Akash Kumar 0001, Thomas Mikolajick, Jens Trommer. 1-6 [doi]
• Adaptive Perception Control for Aerial Robots with Twin Delayed DDPGVeera Venkata Ram Murali Krishna Rao Muvva, Kunjan Theodore Joseph, Kruttidipta Samal, Marilyn Wolf, Santosh Pitla. 1-6 [doi]
• Gradient Boosting-Accelerated Evolution for Multiple-Fault DiagnosisHongfei Wang, Chenliang Luo, Deqing Zou, Hai Jin 0001, Wenjie Cai. 1-6 [doi]
• Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage AmplificationNasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri. 1-6 [doi]
• CASCO: Cascaded Co-Optimization for Holistic Neural Network AccelerationBahador Rashidi, Shan Lu, Kiarash Aghakasiri, Chao Gao, Fred Xuefei Han, Zhisheng Wang, Laiyuan Gong, Fengyu Sun. 1-6 [doi]
• IoT-GRAF: IoT Graph Learning-Based Anomaly and Intrusion Detection Through Multi-Modal Data FusionRozhin Yasaei, Yasamin Moghaddas, Mohammad Abdullah Al Faruque. 1-6 [doi]
• Extending SSD Lifetime via Balancing Layer Endurance in 3D NAND Flash MemorySiyi Huang, Yajuan Du, Yi Fan, Cheng Ji. 1-2 [doi]
• Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional UnitsMuhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich. 1-2 [doi]
• ClassONN: Classification with Oscillatory Neural Networks Using the Kuramoto ModelFilip Sabo, Aida Todri-Sanial. 1-2 [doi]
• X-PIM: Fast Modeling and Validation Framework for Mixed-Signal Processing-in-Memory Using Compressed Equivalent Model in System VerilogIngu Jeong, Jun-Eun Park. 1-6 [doi]
• Dynamic Realization of Multiple Control Toffoli GateAbhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler. 1-6 [doi]
• Fault- Tolerant Cyclic Queuing and Forwarding in Time-Sensitive NetworkingLiwei Zhang, Tong Zhang, Wenxue Wu, Xiaoqin Feng, Guoxi Lin, Fengyuan Ren. 1-6 [doi]
• Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & CompilersMichael T. Niemier, Z. Enciso, M. Sharifi, Xiaobo Sharon Hu, Ian O'Connor, A. Graening, R. Sharma, P. Gupta, Jerónimo Castrillón, João Paulo C. de Lima, A. A. Khan, H. Farzaneh, N. Afroze, Asif Khan, Julien Ryckaert. 1-10 [doi]
• Unearthing the Potential of Spiking Neural NetworksSayeed Shafayet Chowdhury, Adarsh Kumar Kosta, Deepika Sharma, Marco Paul E. Apolinario, Kaushik Roy 0001. 1-6 [doi]
• SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing ScenariosHaoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang 0001. 1-6 [doi]
• Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep LearningRahul Vishwakarma, Amin Rezaei 0001. 1-6 [doi]
• Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen EstimationSeyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram. 1-6 [doi]
• An Isotropic Shift-Pointwise Network for Crossbar-Efficient Neural Network DesignZiyi Guan, Boyu Li, Yuan Ren, Muqun Niu, Hantao Huang, Graziano Chesi, Hao Yu 0001, Ngai Wong. 1-6 [doi]
• Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster BalancingGeorge Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao. 1-2 [doi]
• SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN AcceleratorsJing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran. 1-6 [doi]
• Can Machine Learn Pipeline Leakage?Omid Bazangani, Parisa Amiri-Eliasi, Stjepan Picek, Lejla Batina. 1-6 [doi]
• FlexForge: Efficient Reconfigurable Cloud Acceleration via Peripheral Resource DisaggregationSe-Min Lim, Sang-Woo Jun. 1-6 [doi]
• MicroNAS: Zero-Shot Neural Architecture Search for MCUsYe Qiao, Haocheng Xu, Yifan Zhang, Sitao Huang. 1-2 [doi]
• Scalable Logic Rewriting Using Don't CaresAlessandro Tempia Calvino, Giovanni De Micheli. 1-6 [doi]
• EMAClave: An Efficient Memory Authentication for RISCV EnclavesOmais Pandith, Rafail Psiakis, Johanna Toivanen. 1-6 [doi]
• 12 mJ Per Class On-Device Online Few-Shot Class-Incremental LearningYoga Esa Wibowo, Cristian Cioflan, Thorir Mar Ingolfsson, Michael Hersche, Leo Zhao, Abbas Rahimi, Luca Benini. 1-6 [doi]
• A Read Latency Variation Aware Independent Read Scheme for QLC SSDsDong Huang, Dan Feng 0001, Qiankun Liu, Bo Ding, Wei Zhao, Xueliang Wei, Wei Tong 0001. 1-6 [doi]
• Unleashing the Power of T1-Cells in SFQ Arithmetic CircuitsRassul Bairamkulov, Mingfei Yu, Giovanni De Micheli. 1-2 [doi]
• Reliable Interval Prediction of Minimum Operating Voltage Based on On-Chip Monitors via Conformalized Quantile RegressionYuxuan Yin, Xiaoxiao Wang, Rebecca Chen, Chen He, Peng Li. 1-6 [doi]
• ONE-SA: Enabling Nonlinear Operations in Systolic Arrays For Efficient and Flexible Neural Network InferenceRuiqi Sun, Yinchen Ni, Xin He, Jie Zhao, An Zou. 1-6 [doi]
• RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern GenerationNurun Nahar Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor. 1-6 [doi]
• An Autonomic Resource Allocating SSDDongJoon Lee, Jongin Choe, Chanyoung Park, Kyungtae Kang, Mahmut T. Kandemir, Wonil Choi. 1-6 [doi]
• Microprocessor Design Space Exploration via Space Partitioning and Bayesian OptimizationZijun Jiang, Yangdi Lyu. 1-2 [doi]
• Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic EncryptionFlorian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy. 1-6 [doi]
• Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGATrishna Rajkumar, Johnny Öberg. 1-6 [doi]
• AttBind: Memory-Efficient Acceleration for Long-Range Attention Using Vector-Derived Symbolic BindingWeihong Xu, Jaeyoung Kang 0001, Tajana Rosing. 1-6 [doi]
• TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI HardwareJonas Crols, Guilherme Paim, Shirui Zhao, Marian Verhelst. 1-6 [doi]
• Adaptive DRAM Cache Division for Computational Solid-state DrivesShuaiwen Yu, Zhibing Sha, Chengyong Tang, Zhigang Cai, Peng Tang, Min Huang, Jun Li, Jianwei Liao 0001. 1-6 [doi]
• MNT Bench: Benchmarking Software and Layout Libraries for Field-Coupled NanocomputingSimon Toni Hofmann, Marcel Walter, Robert Wille. 1-2 [doi]
• Securing ISW Masking Scheme Against GlitchesSofiane Takarabt, Javad Bahrami, Mohammad Ebrahimabadi, Sylvain Guilley, Naghmeh Karimi. 1-2 [doi]
• IOMMU Deferred Invalidation Vulnerability: Exploit and DefenseChathura Rajapaksha, Leila Delshadtehrani, Richard Muri, Manuel Egele, Ajay Joshi. 1-6 [doi]
• tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace SamplingTianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng 0001. 1-6 [doi]
• Polynomial Formal Verification of Sequential CircuitsCaroline Dominik, Rolf Drechsler. 1-6 [doi]
• Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital LogicSasan Razmkhah, Robert S. Aviles, Mingye Li, Sandeep Gupta 0001, Peter A. Beerel, Massoud Pedram. 1-6 [doi]
• An Adaptive UAV Scheduling Process to Address Dynamic Mobile Network Demand EfficientlyRuide Cao, Jiao Ye, Jin Zhang, Qian You, Chao Tang, Yan Liu, Yi Wang. 1-6 [doi]
• Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change MemoriesSpyridon Spyridonos, Yiorgos Tsiatouhas. 1-6 [doi]
• Self-Learning and Transfer Across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout SynthesisKaichang Chen, Georges G. E. Gielen. 1-6 [doi]
• FusionArch: A Fusion-Based Accelerator for Point-Based Point Cloud Neural NetworksXueyuan Liu, Zhuoran Song, Guohao Dai, Gang Li, Can Xiao, Yan Xiang, Dehui Kong, Ke Xu, Xiaoyao Liang. 1-6 [doi]
• A Scalable RISC-V Hardware Platform for Intelligent Sensor ProcessingPaul Palomero Bernardo, Patrick Schmid, Oliver Bringmann 0001, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch 0001, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker. 1-5 [doi]
• Cognitive Sensing for Energy-Efficient Edge IntelligenceMinah Lee, Sudarshan Sharma, Wei-chun Wang, Hemant Kumawat, Nael Mizanur Rahman, Saibal Mukhopadhyay. 1-6 [doi]
• BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoostChanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim. 1-6 [doi]
• Decentralized Federated Learning in Partially Connected Networks with Non-IID DataXiaojun Cai, Nanxiang Yu, Mengying Zhao, Mei Cao, Tingting Zhang, Jianbo Lu. 1-6 [doi]
• UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security IncidentsMatthias Stammler, Julian Lorenz, Eric Sax, Jürgen Becker 0001, Matthias Hamann, Patrick Bidinger, Andreas Dewald, Paraskevi Georgouti, Alexios Camarinopoulos, Günter Becker, Klaus Finsterbusch, Maximilian Kirschner, Laurenz Adolph, Carl Philipp Hohl, Maria Rill, Daniel Vonderau, Victor Pazmino Betancourt. 1-6 [doi]
• A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment InterconnectsYunfan Zuo, Yuyang Ye, Hongchao Zhang, Tinghuan Chen, Hao Yan 0002, Longxing Shi. 1-6 [doi]
• An AI-Enabled Framework for Smart Semiconductor ManufacturingKhaled Sidahmed Sidahmed Alamin, Davide Appello, Alessandro Beghi, Nicola Dall'Ora, Fabio Depaoli, Santa Di Cataldo, Franco Fummi, Sebastiano Gaiardelli, Michele Lora, Enrico Macii, Alessio Mascolini, Daniele Pagano, Francesco Ponzio, Gian Antonio Susto, Sara Vinco. 1-6 [doi]
• ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self TestHongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen. 1-6 [doi]
• Circuits Physics Constrained Predictor of Static IR Drop with Limited DataYuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng 0001. 1-2 [doi]
• HW-SW Optimization of DNNs for Privacy-Preserving People Counting on Low-Resolution Infrared ArraysMatteo Risso, Chen Xie, Francesco Daghero, Alessio Burrello, Seyedmorteza Mollaei, Marco Castellano, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari. 1-6 [doi]
• sLET for Distributed Aerospace Landing SystemDamien Chabrol, Guillaume Phavorin, Eric Jenn. 1-2 [doi]
• Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM ArchitectureYintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li, Ying Wang 0001. 1-6 [doi]
• PaLM: Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern RecognitionHongquan He, Guowen Kuang, Qi Sun, Hao Geng. 1-6 [doi]
• Value-Driven Mixed-Precision Quantization for Patch-Based Inference on MicrocontrollersWei Tao, Shenglin He, Kai Lu, Xiaoyang Qu, Guokuan Li, Jiguang Wan, Jianzong Wang, Jing Xiao 0006. 1-6 [doi]
• Tiny- VBF: Resource-Efficient Vision Transformer based Lightweight Beamformer for Ultrasound Single-Angle Plane Wave ImagingT. P. Abdul Rahoof, Vivek Chaturvedi, Mahesh Raveendranatha Panicker, Muhammad Shafique 0001. 1-6 [doi]
• Resilience of Deep Learning Applications: Where We are and Where We Want to GoCristiana Bolchini, Alberto Bosio. 1 [doi]
• COMET: A Cross-Layer Optimized Optical Phase-Change Main Memory ArchitectureFebin Sunny, Amin Shafiee, Benoît Charbonnier, Mahdi Nikdast, Sudeep Pasricha. 1-6 [doi]
• DRAM-Locker: A General-Purpose DRAM Protection Mechanism Against Adversarial DNN Weight AttacksRanyang Zhou, Sabbir Ahmed, Arman Roohi, Adnan Siraj Rakin, Shaahin Angizi. 1-6 [doi]
• Work in Progress: Linear Transformers for TinyMLMoritz Scherer, Cristian Cioflan, Michele Magno, Luca Benini. 1-2 [doi]
• Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural NetworksIlkin Aliyev, Tosiron Adegbija. 1-2 [doi]
• H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual RepresentationsZishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury. 1-6 [doi]
• Zero-Shot Classification Using Hyperdimensional ComputingSamuele Ruffino, Geethan Karunaratne, Michael Hersche, Luca Benini, Abu Sebastian, Abbas Rahimi. 1-2 [doi]
• Derailed: Arbitrarily Controlling DNN Outputs with Targeted Fault Injection AttacksJhon Ordoñez, Chengmo Yang. 1-6 [doi]
• Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural NetworksPaul R. Genssler, Sandy A. Wasif, Miran Wael, Rodion Novkin, Hussam Amrouch. 1-6 [doi]
• Lightweight and Predictable Memory Virtualization on Medium-Size MicrocontrollersStefano Mercogliano, Daniele Ottaviano, Alessandro Cilardo, Marcello Cinque. 1-2 [doi]
• IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix MultiplicationsVasileios Titopoulos, K. Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 1-6 [doi]
• Analog Printed Spiking Neuromorphic CircuitPriyanjana Pal, Haibin Zhao, Maha Shatta, Michael Hefenbrock, Sina Bakhtavari Mamaghani, Sani R. Nassif, Michael Beigl, Mehdi B. Tahoori. 1-6 [doi]
• EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-ProcessingYuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani. 1-6 [doi]
• A Mapping of Triangular Block Interleavers to DRAM for Optical Satellite CommunicationLukas Steiner, Timo Lehnigk-Emden, Markus Fehrenz, Norbert Wehn. 1-2 [doi]
• LaVA: An Effective Layer Variation Aware Bad Block Management for 3D CT NAND FlashShuhan Bai, You Zhou, Fei Wu, Changsheng Xie, Tei-Wei Kuo, Chun Jason Xue. 1-6 [doi]
• PACE: A Piece-Wise Approximate and Configurable Floating - Point Divider for Energy - Efficient ComputingChenyi Wen, Haonan Du, Zhengrui Chen, Li Zhang, Qi Sun, Cheng Zhuo. 1-6 [doi]
• Motivating the Use of Machine-Learning for Improving Timing Behaviour of Embedded Mixed-Criticality SystemsVikash Kumar, Behnaz Ranjbar, Akash Kumar 0001. 1-2 [doi]
• Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMVChi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini. 1-6 [doi]
• Cuper: Customized Dataflow and Perceptual Decoding for Sparse Matrix-Vector Multiplication on HBM-Equipped FPGAsEnxin Yi, Yiru Duan, Yinuo Bai, Kang Zhao, Zhou Jin 0001, Weifeng Liu 0002. 1-6 [doi]
• Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural NetworksXinkuang Geng, Siting Liu 0001, Jianfei Jiang 0001, Kai Jiang, Honglan Jiang. 1-6 [doi]
• ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic GatesTarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann. 1-2 [doi]
• Device-Aware Diagnosis for Yield Learning in RRAMsHanzhi Xun, Moritz Fieback, Sicong Yuan, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui. 1-6 [doi]
• ViTA: A Highly Efficient Dataflow and Architecture for Vision TransformersChunyun Chen, Lantian Li, Mohamed M. Sabry Aly. 1-6 [doi]
• SCGen: A Versatile Generator Framework for Agile Design of Stochastic CircuitsZexi Li, Haoran Jin, Kuncai Zhong, Guojie Luo, Runsheng Wang, Weikang Qian. 1-6 [doi]
• HaLo-FL: Hardware-Aware Low-Precision Federated LearningYeshwanth Venkatesha, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda. 1-6 [doi]
• DyPIM: Dynamic-Inference-Enabled Processing - In-Memory AcceleratorTongxin Xie, Tianchen Zhao, Zhenhua Zhu, Xuefei Ning, Bing Li, Guohao Dai, Huazhong Yang, Yu Wang 0002. 1-6 [doi]
• Demonstrating Post-Quantum Remote Attestation for RISC-V DevicesMaximilian Barger, Marco Brohet, Francesco Regazzoni 0001. 1-2 [doi]
• AFPR-CIM: An Analog-Domain Floating-Point RRAM -based Compute- In- Memory Architecture with Dynamic Range Adaptive FP-ADCHaobo Liu, Zhengyang Qian, Wei Wu, Hongwei Ren, Zhiwei Liu, Leibin Ni. 1-6 [doi]
• TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack Through Frequency-Triggered Key GenerationJianfeng Wang, Shuwen Deng, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li. 1-6 [doi]
• Automated Hardware Security Countermeasure Integration Inside High Level SynthesisAmalia-Artemis Koufopoulou, Athanasios Papadimitriou, Mihalis Psarakis, David Hély. 1-2 [doi]
• Training Better CNN Models for 3-D Capacitance Extraction with Neural Architecture SearchHaoyuan Li, Dingcheng Yang, Wenjian Yu. 1-2 [doi]
• A Hardware Accelerated Autoencoder for RF Communication Using Short-Time-Fourier- Transform Assisted Convolutional Neural NetworkKuchul Jung, Jongseok Woo, Saibal Mukhopadhyay. 1-6 [doi]
• Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metricsDonger Luo, Qi Sun, Qi Xu, Tinghuan Chen, Hao Geng. 1-6 [doi]
• ECM: Improving IoT Throughput with Energy-Aware Connection ManagementFatemeh Ghasemi, Lukas Liedtke, Magnus Jahre. 1-6 [doi]
• Breaking the Memory Wall with a Flexible Open-Source L1 Data-CacheDavy Million, Noelia Oliete-Escuín, César Fuguet. 1-2 [doi]
• LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free OperationSamuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini. 1-6 [doi]
• Design Automation for Cyber-Physical Production Systems: Lessons Learned from the DeFacto ProjectMichele Lora, Sebastiano Gaiardelli, Chanwook Oh, Stefano Spellini, Pierluigi Nuzzo 0002, Franco Fummi. 1-6 [doi]
• HygHD: Hyperdimensional Hypergraph LearningJaeyoung Kang 0001, You Hak Lee, Minxuan Zhou, Weihong Xu, Tajana Rosing. 1-6 [doi]
• Deep Quasi-Periodic Priors: Signal Separation in Wearable Systems with Limited DataMahya Saffarpour, Kourosh Vali, Weitai Qian, Begum Kasap, Diana L. Farmer, Aijun Wang, Soheil Ghiasi. 1-2 [doi]
• PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory AcceleratorsXinyu Wang, Xiaotian Sun, Yinhe Han 0001, Xiaoming Chen 0003. 1-2 [doi]
• Dynamic Per-Flow Queues for TSN SwitchesWenxue Wu, Zhen Li, Tong Zhang, Xiaoqin Feng, Liwei Zhang, Xuelong Qi, Fengyuan Ren. 1-2 [doi]
• SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box MicroarchitecturesNajmeh Nazari, Behnam Omidi, Chongzhou Fang, Hosein Mohammadi Makrani, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Khaled N. Khasawneh. 1-6 [doi]
• CALLOC: Curriculum Adversarial Learning for Secure and Robust Indoor LocalizationDanish Gufran, Sudeep Pasricha. 1-6 [doi]
• PIMLC: Logic Compiler for Bit-Serial Based PIMChenyu Tang, Chen Nie, Weikang Qian, Zhezhi He. 1-6 [doi]
• Efficient Design of a Hyperdimensional Processing Unit for Multi-Layer CognitionMohamed Ibrahim, Youbin Kim, Jan M. Rabaey. 1-6 [doi]
• Improvement of Mixed Track - Height Standard-Cell PlacementAndrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon. 1-6 [doi]
• TitanCFI: Toward Enforcing Control-Flow Integrity in the Root -of- TrustEmanuele Parisi, Alberto Musa, Simone Manoni, Maicol Ciani, Davide Rossi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva. 1-6 [doi]
• Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable ProcessorsYehuda Kra, Naama Kra, Adam Teman. 1-6 [doi]
• Automated Traffic Scenario Description Extraction Using Video TransformersAron Harder, Madhur Behl. 1-6 [doi]
• Embedding Hardware Approximations in Discrete Genetic-Based Training for Printed MLPsFlorentia Afentaki, Michael Hefenbrock, Georgios Zervakis 0001, Mehdi B. Tahoori. 1-6 [doi]
• Low Power and Temperature- Resilient Compute-In-Memory Based on Subthreshold-FeFETYifei Zhou, Xuchu Huang, Jianyi Yang, Kai Ni 0004, Hussam Amrouch, Cheng Zhuo, Xunzhao Yin. 1-6 [doi]
• A Novel Multi-Objective Optimization Framework for Analog Circuit CustomizationMutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta 0001. 1-2 [doi]
• A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and SizingSouradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu 0001, Yaoyao Jia, David Z. Pan. 1-6 [doi]
• CPF: A Cross-Layer Prefetching Framework for High-Density Flash-Based StorageLongfei Luo, Han Wang, Dingcui Yu, Yina Lv, Liang Shi. 1-6 [doi]
• LLM-Based Processor Verification: A Case Study for Neuronnorphic ProcessorChao Xiao, Yifei Deng, Zhijie Yang, Renzhi Chen, Hong Wang, Jingyue Zhao, Huadong Dai, Lei Wang, Yuhua Tang, Weixia Xu. 1-6 [doi]
• Three Sidekicks to Support Spectre CountermeasuresMarkus Krausz, Jan Philipp Thoma, Florian Stolz, Marc Fyrbiak, Tim Güneysu. 1-6 [doi]
• A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity ComputationQingrong Huang, Hamza Errahmouni Barkam, Zeyu Yang, Jianyi Yang, Thomas Kämpfe, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Mohsen Imani, Cheng Zhuo, Xunzhao Yin. 1-6 [doi]
• Quantum State Preparation Using an Exact CNOT Synthesis FormulationHanyu Wang, Jason Cong, Giovanni De Micheli. 1-6 [doi]
• Back to the Future: Reversible Runtime Neural Network Pruning for Safe Autonomous SystemsDanny Abraham, Biswadip Maity, Bryan Donyanavard, Nikil D. Dutt. 1-6 [doi]
• Multi-Agent Reinforcement Learning for Thermally-Restricted Performance Optimization on ManycoresHeba Khdr, Mustafa Enes Batur, Kanran Zhou, Mohammed Bakr Sikal, Jörg Henkel. 1-6 [doi]
• Trace-Enabled Timing Model Synthesis for ROS2-based Autonomous ApplicationsHazem Abaza, Debayan Roy, Shiqing Fan, Selma Saidi, Antonios Motakis. 1-6 [doi]
• AI Models for Edge Computing: Hardware-aware Optimizations for EfficiencyHai Helen Li. 1 [doi]
• Decoupled Access-Execute Enabled DVFS for TinyML Deployments on STM32 MicrocontrollersElisavet Lydia Alvanaki, Manolis Katsaragakis, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris. 1-6 [doi]
• MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge ApplicationsTousif Rahman, Gang Mao, Sidharth Maheshwari, Rishad A. Shafik, Alex Yakovlev. 1-6 [doi]
• CRONuS: Circuit Rapid Optimization with Neural SimulatorYoungmin Oh, Doyun Kim, Yoon Hyeok Lee, Bosun Hwang. 1-6 [doi]
• A Stakeholder Analysis of Operational Design Domains of Automated Driving SystemsMarcel Aguirre Mehlhorn, Hauke Dierend, Andreas Richter, Yuri A. W. Shardt. 1-2 [doi]
• Parallel Multi-Objective Bayesian Optimization Framework for CGRA MicroarchitectureBing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu, Song Chen, Yi Kang. 1-6 [doi]
• Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNsMingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo. 1-6 [doi]
• Towards Cycle-based Shuttling for Trapped-Ion Quantum Computers (Extended Abstract)Daniel Schönberger, Stefan Hillmich, Matthias Brandl, Robert Wille. 1-2 [doi]
• Harnessing ML Privacy by Design Through Crossbar Array Non-IdealitiesMd. Shohidul Islam, Sankha Baran Dutta, Andres Marquez, Ihsen Alouani, Khaled N. Khasawneh. 1-2 [doi]
• CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector MergingTaixin Li, Hongtao Zhong, Juejian Wu, Thomas Kämpfe, Kai Ni 0004, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li. 1-6 [doi]
• ADAssure: Debugging Methodology for Autonomous Driving Control AlgorithmsAndrew Roberts, Mohammad Reza Heidari Iman, Mauro Bellone, Tara Ghasempouri, Jaan Raik, Olaf Maennel, Mohammad Hamad, Sebastian Steinhorst. 1-6 [doi]
• Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine TransformationsSoyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori. 1-6 [doi]
• Para-ZNS: Improving Small-Zone ZNS SSDs Parallelism Through Dynamic Zone MappingZhenhua Tan, Linbo Long, Jingcheng Shen, Congming Gao, Renping Liu, Yi Jiang. 1-6 [doi]
• Context-aware Multi-Model Object Detection for Diversely Heterogeneous Compute SystemsJustin Davis, Mehmet E. Belviranli. 1-6 [doi]
• Environmental Microchanges in WiFi SensingCristian Turetta, Philipp H. Kindt, Alejandro Masrur, Samarjit Chakraborty, Graziano Pravadelli, Florenc Demrozi. 1-2 [doi]
• A Hybrid Approach to Reverse Engineering on Combinational CircuitsWuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang. 1-2 [doi]
• A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital SynthesisMathieu Toubeix, Eric Guthmuller, Adrian Evans, Tristan Meunier. 1-2 [doi]
• MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core ProcessorBingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng, Wei Guo. 1-6 [doi]
• JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum CircuitsSiyan Chen, Rongliang Fu, Junying Huang, Zhimin Zhang 0004, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan. 1-6 [doi]
• A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN TrainingSami Ben Ali, Silviu-Ioan Filip, Olivier Sentieys. 1-6 [doi]
• High Throughput Hardware Accelerated CoreSight Trace DecodingMatthew Edwin Weingarten, Nora Hossle, Timothy Roscoe. 1-6 [doi]
• Algorithm-Hardware Co-Design for Energy-Efficient A/D Conversion in ReRAM-Based AcceleratorsChenguang Zhang, Zhihang Yuan, Xingchen Li, Guangyu Sun 0003. 1-6 [doi]
• MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix MultiplicationMatteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini. 1-6 [doi]
• Approximation Algorithm for Noisy Quantum Circuit SimulationMingyu Huang, Ji Guan, Wang Fang, Mingsheng Ying. 1-6 [doi]
• Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCsKhalil Esper, Stefan Wildermann, Jürgen Teich. 1-2 [doi]
• End-to-End Latency Optimization of Thread Chains Under the DDS Publish/Subscribe MiddlewareGerlando Sciangula, Daniel Casini, Alessandro Biondi 0001, Claudio Scordino. 1-6 [doi]
• A Configurable Approximate Multiplier for CNNs Using Partial Product SpeculationXiaolu Hu, Ao Liu, Xinkuang Geng, Zizhong Wei, Kai Jiang, Honglan Jiang. 1-6 [doi]
• DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware ArchitectureJianfeng Song, Rongjian Liang, Yu Gong, Bo Yuan 0001, Jiang Hu. 1-6 [doi]
• SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum- Flux - Parametron Superconducting CircuitsYanyue Xie, Peiyan Dong, Geng Yuan, Zhengang Li, Masoud Zabihi, Chao Wu, Sung-En Chang, Xufeng Zhang, Xue Lin, Caiwen Ding, Nobuyuki Yoshikawa, Olivia Chen, Yanzhi Wang. 1-6 [doi]
• High-Performance Feature Extraction for GPU -Accelerated ORB-SLAMxFilippo Muzzini, Nicola Capodieci, Roberto Cavicchioli, Benjamin Rouxel. 1-2 [doi]
• NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN AcceleratorMohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh. 1-6 [doi]
• Late Breaking Results: Iterative Design Automation for Train Control with Hybrid Train DetectionStefan Engels, Robert Wille. 1-2 [doi]
• Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning WorkloadsHarsh Sharma, Gaurav Narang, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande. 1-6 [doi]
• MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing ProcessorsVasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran. 1-6 [doi]
• Corporate Governance and Management of AI-Driven Product Development: Vehicle AutomationWilliam H. Widen, Marilyn Claire Wolf. 1-6 [doi]
• Electrostatics-Based Analytical Global Placement for Timing OptimizationZhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang. 1-6 [doi]
• An Efficient Hypergraph Partitioner under Inter - Block Interconnection ConstraintsBenzheng Li, Hailong You, Shunyang Bi, YuMing Zhang. 1-6 [doi]
• Sava: A Spatial- and Value-Aware Accelerator for Point Cloud TransformerXueyuan Liu, Zhuoran Song, Xiang Liao, Xing Li, Tao Yang, Fangxin Liu, Xiaoyao Liang. 1-6 [doi]
• Discovering Efficient Fused Layer Configurations for Executing Multi-Workloads on Multi-Core NPUsYounghyun Lee, Hyejun Kim, Yongseung Yu, Myeongjin Cho, Jiwon Seo 0002, Yongjun Park 0001. 1-6 [doi]
• ViT- ToGo: Vision Transformer Accelerator with Grouped Token PruningSeungju Lee, Kyumin Cho, Eunji Kwon, Sejin Park, Seojeong Kim, Seokhyeong Kang. 1-6 [doi]
• DeepSeq: Deep Sequential Circuit LearningSadaf Khan, Zhengyuan Shi, Min Li, Qiang Xu. 1-2 [doi]
• Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix FactorizationDaniel Bochen Tan, Shuohao Ping, Jason Cong. 1-6 [doi]
• Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEPTim Henkes, Steffen Reith, Marc Stöttinger, Norbert Herfurth, Goran Panic, Julian Wälde, Fabian Buschkowski, Pascal Sasdrich, Christoph Lüth, Milan Funck, Tuba Kiyan, Arnd Weber, Detlef Boeck, René Rathfelder, Torsten Grawunder. 1-6 [doi]
• On Gate Flip Errors in Computing-In-MemoryZamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu. 1-6 [doi]
• OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge DistillationRuidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li. 1-6 [doi]
• CLAST: Cross-Layer Approximate High-Level Synthesis with Configurable Approximate Three-Operand AddersJian Shi, Wenjing Zhang, Weikang Qian. 1-2 [doi]
• PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-Time Memory Diagnostic Data Compression in Automotive SoCsSunyoung Park, HyunJi Kim, Hana Kim, Ji-Hoon Kim. 1-6 [doi]
• Design Automation for Organs-on-ChipMaria Emmerich, Philipp Ebner, Robert Wille. 1-6 [doi]
• Navigating the Unknown: Uncertainty-Aware Compute-in-Memory Autonomy of Edge RoboticsNastaran Darabi, Priyesh Shukla, Dinithi Jayasuriya, Divake Kumar, Alex C. Stutts, Amit Ranjan Trivedi. 1-6 [doi]
• PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT ProcessorsAlessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini. 1-6 [doi]
• Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit RepresentationHo-Jin Lee, Kyeong-Jun Lee, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang, Jae-Yoon Sim. 1-2 [doi]
• Detecting Backdoor Attacks in Black-Box Neural Networks through Hardware Performance CountersManaar Alam, Yue Wang 0055, Michail Maniatakos. 1-6 [doi]
• Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source ProcessorsGideon Mohr, Marco Guarnieri, Jan Reineke 0001. 1-6 [doi]
• The METASAT Model-Based Engineering Workflow and Digital Twin ConceptAlejandro J. Calderón, Irune Yarza, Stefano Sinisi, Lorenzo Lazzara, Valerio Di Valerio, Giulia Stazi, Leonidas Kosmidis, Matina Maria Trompouki, Alessandro Ulisse, Aitor Amonarriz, Peio Onaindia. 1-6 [doi]
• FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech TranslationIan O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand 0002, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux. 1-6 [doi]
• FeReX: A Reconfigurable Design of Multi-Bit Ferroelectric Compute-in-Memory for Nearest Neighbor SearchZhicheng Xu, Che-Kai Liu, Chao Li, Ruibin Mao, Jianyi Yang, Thomas Kämpfe, Mohsen Imani, Can Li, Cheng Zhuo, Xunzhao Yin. 1-6 [doi]
• Design Automation for Quantum Computing: Intermediate Stage Report of the ERC Consolidator Grant "DAQC"Robert Wille. 1-6 [doi]
• OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual ComputingMehrdad Morsali, Sepehr Tabrizchi, Deniz Najafi, Mohsen Imani, Mahdi Nikdast, Arman Roohi, Shaahin Angizi. 1-6 [doi]
• Performance Analysis and Optimizations of Matrix Multiplications on ARMv8 ProcessorsHucheng Liu, Shaohuai Shi, Xuan Wang, Zoe L. Jiang, Qian Chen. 1-6 [doi]
• Efficient Spectral-Aware Power Supply Noise Analysis for Low-Power Design VerificationYinuo Bai, Xiaoyu Yang, Yicheng Lu, Dan Niu, Cheng Zhuo, Zhou Jin 0001, Weifeng Liu 0002. 1-6 [doi]
• DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless SystemsSepehr Tabrizchi, Shaahin Angizi, Arman Roohi. 1-6 [doi]
• SELCC: Enhancing MLC Reliability and Endurance with Single-Cell Error Correction CodesYujin Lim, Dongwhee Kim, Jungrae Kim. 1-6 [doi]
• BoolGebra: Attributed Graph-Learning for Boolean Algebraic ManipulationYingjie Li, Anthony Agnesina, Yanqing Zhang 0002, Haoxing Ren, Cunxi Yu. 1-2 [doi]
• Programmable EM Sensor Array for Golden-Model Free Run-Time Trojan Detection and LocalizationHanqiu Wang, Max Panoff, Zihao Zhan, Shuo Wang, Christophe Bobda, Domenic Forte. 1-6 [doi]
• Deductive Formal Verification of Synthesizable, Transaction-Level Hardware Designs Using CoqTobias Strauch. 1-6 [doi]
• Auto-tuning Multi-GPU High-Fidelity Numerical Simulations for Urban Air MobilityKonstantina Koliogeorgi, George Anagnostopoulos, Gerardo Zampino, Marcial Sanchis, Ricardo Vinuesa, Sotirios Xydis. 1-6 [doi]
• Fluid Dynamic DNNs for Reliable and Adaptive Distributed Inference on Edge DevicesLei Xun, Mingyu Hu, Hengrui Zhao, Amit Kumar Singh 0002, Jonathon Hare, Geoff V. Merrett. 1-2 [doi]
• Intelligent Hybrid Memory Scheduling Based on Page Pattern RecognitionYanjie Zhen, Weining Chen, Wei Gao, Ju Ren 0001, Kang Chen, Yu Chen 0004. 1-2 [doi]
• HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering SystemShengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu 0002, Huawei Li, Xiaowei Li. 1-6 [doi]
• Shared Cache Analysis Under Preemptive SchedulingThilo L. Fischer, Heiko Falk. 1-6 [doi]
• Reconfigurable Frequency Multipliers Based on Complementary Ferroelectric TransistorsHaotian Xu, Jianyi Yang, Cheng Zhuo, Thomas Kämpfe, Kai Ni 0004, Xunzhao Yin. 1-6 [doi]
• Optimizing Ciphertext Management for Faster Fully Homomorphic Encryption ComputationEduardo Chielle, Oleg Mazonka, Michail Maniatakos. 1-6 [doi]
• On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG AnalysisMatteo Antonio Scrugli, Paola Busia, Gianluca Leone, Paolo Meloni. 1-6 [doi]
• Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy ModelJingyu Jia, Jianwang Zhai, Kang Zhao. 1-2 [doi]
• Model-Driven Feature Engineering for Data-Driven Battery SOH ModelKhaled Alamin, Daniele Jahier Pagliari, Yukai Chen, Enrico Macii, Sara Vinco, Massimo Poncino. 1-6 [doi]
• SpecHD: Hyperdimensional Computing Framework for FPGA-Based Mass Spectrometry ClusteringSumukh Pinge, Weihong Xu, Jaeyoung Kang 0001, Tianqi Zhang, Niema Moshiri, Wout Bittremieux, Tajana Rosing. 1-6 [doi]
• Full-Stack Optimization for CAM-Only DNN InferenceJoão Paulo C. de Lima, Asif Ali Khan, Luigi Carro, Jerónimo Castrillón. 1-6 [doi]
• MultimodalHD: Federated Learning Over Heterogeneous Sensor Modalities using Hyperdimensional ComputingQuanling Zhao, Xiaofan Yu, Shengfan Hu, Tajana Rosing. 1-6 [doi]
• SenseDSE: Sensitivity-Based Performance Evaluation for Design Space Exploration of MicroarchitectureZheng Wu, Xiaoling Yi, Li Shang, Fan Yang. 1-6 [doi]
• XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software SystemsTobias Dörr, Florian Schade, Jürgen Becker 0001, Georgios Keramidas, Nikos Petrellis, Vasilios I. Kelefouras, Michail Mavropoulos, Konstantinos Antonopoulos, Christos P. Antonopoulos, Nikolaos S. Voros, Alexander Ahlbrecht, Wanja Zaeske, Vincent Janson, Phillip Nöldeke, Umut Durak, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Clemens Reichmann, Andreas Sailer, Raphael Weber, Thomas Wilhelm 0005, Wolfgang Gabler, Katrin Weiden, Xavier Anzuela Recasens, Sakir Sezer, Fahad Siddiqui 0001, Rafiullah Khan, Kieran McLaughlin, Sena Yengec Tasdemir, Balmukund Sonigara, Henry Hui, Esther Soriano Viguer, Aridane Alvarez Suarez, Vicente Nicolau Gallego, Manuel Muñoz Alcobendas, Miguel Masmano Tello. 1-6 [doi]
• Accelerating Chaining in Genomic Analysis Using RISC- V Custom InstructionsKisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran. 1-6 [doi]
• Heterogeneous Static Timing Analysis with Advanced Delay CalculatorZizheng Guo, Tsung-Wei Huang, Zhou Jin 0001, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang 0001. 1-6 [doi]
• Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform AcceleratorJianan Wen, Andrea Baroni, Eduardo Perez, Max Uhlmann, Markus Fritscher, Karthik KrishneGowda, Markus Ulbricht 0002, Christian Wenger, Milos Krstic. 1-6 [doi]
• Pipette: Automatic Fine-Grained Large Language Model Training Configurator for Real-World ClustersJinkyu Yim, Jaeyong Song, Yerim Choi, Jaebeen Lee, Jaewon Jung 0001, Hongsun Jang, Jinho Lee. 1-6 [doi]
• PURSE: Property Ordering Using Runtime Statistics for Efficient Multi - Property VerificationSourav Das, Aritra Hazra, Pallab Dasgupta, Sudipta Kundu, Himanshu Jain. 1-6 [doi]
• Sparrow: Flexible Memory Deduplication in Android Systems with Similar-Page AwarenessGuangyu Wei, Changlong Li, Rui Xu 0013, Qingfeng Zhuge, Edwin H.-M. Sha. 1-6 [doi]
• SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data SpaceFrancesco Regazzoni 0001, Gergely Ács, Albert Zoltan Aszalos, Christos Avgerinos, Nikolaos Bakalos, Josep Lluis Berral, Joppe W. Bos, Marco Brohet, Andrés G. Castillo Sanz, Gareth T. Davies, Stefanos Florescu, Pierre-Elisée Flory, Alberto Gutierrez-Torre, Evangelos Haleplidis, Alice Héliou, Sotirios Ioannidis, Alexander Islam El-Kady, Katarzyna Kapusta, Konstantina Karagianni, Pieter Kruizinga, Kyrian Maat, Zoltán Ádám Mann, Kalliopi Mastoraki, SeoJeong Moon, Maja Nisevic, Balázs Pejó, Kostas Papagiannopoulos, Vassilis Paliouras, Paolo Palmieri 0001, Francesca Palumbo, Juan Carlos Pérez Baun, Péter Pollner, Eduard Porta-Pardo, Luca Pulina, Muhammad Ali Siddiqi, Daniela Spajic, Christos Strydis, Georgios Tasopoulos, Vincent Thouvenot, Christos Tselios, Apostolos P. Fournaris. 1-4 [doi]
• Beyond Random Inputs: A Novel ML-Based Hardware FuzzingMohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi. 1-6 [doi]
• LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGARoberto Bosio, Giovanni Brignone, Filippo Minnella, M. Usman Jamal, Luciano Lavagno. 1-2 [doi]
• A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System LevelManfred Schlägl, Moritz Stockinger, Daniel Große. 1-6 [doi]
• Towards Forward-Only Learning for Hyperdimensional ComputingHyunsei Lee, Hyukjun Kwon, Jiseung Kim 0005, Seohyun Kim, Mohsen Imani, Yeseong Kim. 1-2 [doi]
• RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital SignatureXinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Jun Han 0003. 1-6 [doi]
• Using Formal Verification Methods for Optimization of Circuits Under External ConstraintsDaniel Große, Lucas Klemmer, Dominik Bonora. 1-6 [doi]
• ARTmine: Automatic Association Rule Mining with Temporal Behavior for Hardware VerificationMohammad Reza Heidari Iman, Gert Jervan, Tara Ghasempouri. 1-6 [doi]
• A Transistor Level Relational Semantics for Electrical Rule Checking by SMT SolvingOussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne. 1-6 [doi]
• Algorithm to Technology Co-Optimization for CiM-Based Hyperdimensional ComputingMahta Mayahinia, Simon Thomann, Paul R. Genssler, Christopher Münch, Hussam Amrouch, Mehdi B. Tahoori. 1-6 [doi]
• Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated ProcessesBharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb. 1-6 [doi]
• TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order ReductionPengju Chen, Dan Niu, Zhou Jin 0001, Changyin Sun, Qi Li, Hao Yan. 1-6 [doi]
• Resource-Efficient Heterogenous Federated Continual Learning on EdgeZhao Yang, Shengbing Zhang, Chuxi Li, Haoyang Wang 0014, Meng Zhang. 1-6 [doi]
• EvilCS: An Evaluation of Information Leakage through Context Switching on Security EnclavesAruna Jayasena, Richard Bachmann, Prabhat Mishra. 1-6 [doi]
• Real-Time Multi-Person Identification and Tracking via HPE and IMU Data FusionMirco De Marchi, Cristian Turetta, Graziano Pravadelli, Nicola Bombieri. 1-6 [doi]
• S-LGCN: Software-Hardware Co-Design for Accelerating LightGCNShun Li, Ruiqi Chen 0001, Enhao Tang, Yajing Liu, Jing Yang, Kun Wang. 1-6 [doi]
• Responsible Artificial Intelligence Systems: From Trustworthiness to GovernanceFramcisco Herrera. 1-2 [doi]
• Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space OptimizationJaemin Seo, Sejin Park 0001, Seokhyeong Kang. 1-6 [doi]
• Formal Verification of Booth Radix-8 and Radix-16 MultipliersMertcan Temel. 1-6 [doi]
• WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAPTuo Dai, Bizhao Shi, Guojie Luo. 1-6 [doi]
• DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and InferenceLorenzo Sonnino, Shaswot Shresthamali, Yuan He 0002, Masaaki Kondo. 1-6 [doi]
• Computational and Storage Efficient Quadratic Neurons for Deep Neural NetworksChuangtao Chen 0001, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li. 1-6 [doi]
• Towards SEU Fault Propagation Prediction with Spatio-Temporal Graph Convolutional NetworksLi Lu, Junchao Chen, Markus Ulbricht 0002, Milos Krstic. 1-2 [doi]
• LLM-Guided Formal Verification Coupled with Mutation TestingMuhammad Hassan 0002, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha 0001, Rolf Drechsler. 1-2 [doi]
• BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear SystemsLunshuai Pan, Pushen Zuo, Yubiao Luo, Zhong Sun, Ru Huang 0001. 1-6 [doi]
• High-Performance Data Mapping for BNNs on PCM-Based Integrated PhotonicsTaha Shahroodi, Raphael Cardoso, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui. 1-6 [doi]
• Statistical Profiling of Micro-Architectural Traces and Machine Learning for Spectre Detection: A Systematic EvaluationMai Al-Zu'bi, Georg Weissenbacher. 1-6 [doi]
• Lightweight Instrumentation for Accurate Performance Monitoring in RTOSesBruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis 0001, Luca Cassano, Marco Ottavi. 1-2 [doi]
• Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution EngineMattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, Maya B. Gokhale. 1-2 [doi]
• Out-of-Distribution Detection Using Power-Side Channels for Improving Functional Safety of Neural Network FPGA AcceleratorsVincent Meyers, Dennis Gnad, Mehdi Baradaran Tahoori. 1-2 [doi]
• PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip SystemsXing Huang, Jiaxuan Wang, Zhiwen Yu 0001, Bin Guo, Tsung-Yi Ho, Ulf Schlichtmann, Krishnendu Chakrabarty. 1-6 [doi]
• VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model CountingChang Meng, Hanyu Wang, Yuqi Mai, Weikang Qian, Giovanni De Micheli. 1-6 [doi]
• Robustness Evaluation of Localization Techniques for Autonomous RacingTian Yi Lim, Edoardo Ghignone, Nicolas Baumann, Michele Magno. 1-2 [doi]
• Towards Scalable GPU System with Silicon Photonic ChipletChengeng Li, Fan Jiang, Shixi Chen, Xianbin Li, Jiaqi Liu, Wei Zhang, Jiang Xu. 1-6 [doi]
• Hidden Cost of Circuit Design with RFETsSajjad Parvin, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler. 1-2 [doi]
• Learning Circuit Placement Techniques Through Reinforcement Learning with Adaptive RewardsLuke Vassallo, Josef Bajada. 1-6 [doi]
• FLInt: Exploiting Floating Point Enabled Integer Arithmetic for Efficient Random Forest InferenceChristian Hakert, Kuan-Hsun Chen, Jian-Jia Chen. 1-2 [doi]
• TT-SNN: Tensor Train Decomposition for Efficient Spiking Neural Network TrainingDonghyun Lee, Ruokai Yin, Youngeun Kim, Abhishek Moitra, Yuhang Li, Priyadarshini Panda. 1-6 [doi]
• VeriBug: An Attention-Based Framework for Bug Localization in Hardware DesignsGiuseppe Stracquadanio, Sourav Medya, Stefano Quer, Debjit Pal. 1-2 [doi]
• Combining Formal Verification and Testing for Debugging of Arithmetic CircuitsJiteshri Dasari, Maciej J. Ciesielski. 1-6 [doi]
• In-Field Detection of Small Delay Defects and Runtime Degradation Using On-Chip SensorsSeyedeh Maryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori. 1-2 [doi]
• Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-Preserving Federated Learning AggregationWenye Liu, Nazim Altar Koca, Chip-Hong Chang. 1-6 [doi]
• Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net ModelSeunggyu Lee, Daijoon Hyun, Younggwang Jung, Gangmin Cho, Youngsoo Shin. 1-6 [doi]
• Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLSHanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu. 1-6 [doi]
• A Framework for Designing Scalable Gaussian Belief Propagation Accelerators for use in SLAMOmar Sharif, Christos-Savvas Bouganis. 1-2 [doi]
• DNA-Based Similar Image Retrieval via Triplet Network-Driven EncoderTakefumi Koike, Hiromitsu Awano, Takashi Sato. 1-2 [doi]
• Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon PhotonicsSalma Afifi, Febin Sunny, Mahdi Nikdast, Sudeep Pasricha. 1-6 [doi]
• GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy ReductionYibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han 0001. 1-6 [doi]
• 2SR: Immediate Interrupt Service Routine on RISC-V MCU to Control mmWave RF TransceiversJimin Lee, Sangwoo Park, Junho Huh, Sanghyo Jeong, InHwan Kim, Jae Min Kim. 1-2 [doi]
• Technology-Aware Logic Synthesis for Superconducting ElectronicsRassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli. 1-6 [doi]
• Analog Transistor Placement Optimization Considering Nonlinear Spatial VariationsSupriyo Maji, Sungyoung Lee, David Z. Pan. 1-6 [doi]
• Parallel Gröbner Basis Rewriting and Memory Optimization for Efficient Multiplier VerificationHongduo Liu, Peiyu Liao, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu 0001. 1-6 [doi]
• FARe: Fault-Aware GNN Training on ReRAM-Based PIM AcceleratorsPratyush Dhingra, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Ananth Kalyanaraman, Partha Pratim Pande. 1-6 [doi]
• DACO: Pursuing Ultra-low Power Consumption via DNN-Adaptive CPU-GPU CO-optimization on Mobile DevicesYushu Wu, Chao Wu, Geng Yuan, Yanyu Li, Weichao Guo, Jing Rao, Xipeng Shen, Bin Ren, Yanzhi Wang. 1-2 [doi]
• Efficient Exploration of Cyber-Physical System Architectures Using Contracts and Subgraph IsomorphismYifeng Xiao, Chanwook Oh, Michele Lora, Pierluigi Nuzzo 0002. 1-6 [doi]
• AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCsThomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia 0002, Alessandro Biondi 0001, Luca Benini. 1-6 [doi]
• Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process NodesHandong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim. 1-6 [doi]
• Learning Assisted Post-Manufacture Testing and Tuning of RRAM-Based DNNs for Yield RecoveryKwondo Ma, Anurup Saha, Chandramouli N. Amarnath, Abhijit Chatterjee. 1-6 [doi]
• Adaptive ODE Solvers for Timed Data Flow Models in SystemC-AMSAlexandra Küster, Rainer Dorsch, Christian Haubelt. 1-6 [doi]
• CBTune: Contextual Bandit Tuning for Logic SynthesisFangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu 0001. 1-6 [doi]
• HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit RecognitionPaul R. Genssler, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch. 1-2 [doi]
• 3PIM: An Automated, Analytic and Accurate Processing-in-Memory OffloaderQingcai Jiang, Shaojie Tan, Junshi Chen, Hong An. 1-6 [doi]
• A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid NetworkSiyu Zhang, Wendong Mao, Huihong Shi, Zhongfeng Wang 0001. 1-6 [doi]
• DropHD: Technology/Algorithm Co-Design for Reliable Energy-Efficient NVM-Based Hyper-Dimensional Computing Under Voltage ScalingPaul R. Genssler, Mahta Mayahinia, Simon Thomann, Mehdi B. Tahoori, Hussam Amrouch. 1-6 [doi]
• $\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR MergingAditya S. Gangwar, Prathamesh Nitin Tanksale, Shirshendu Das, Sudeepta Mishra. 1-6 [doi]
• A Golden-Free Formal Method for Trojan Detection in Non-Interfering AcceleratorsAnna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz. 1-6 [doi]
• REDCAP: Reconfigurable RFET-Based Circuits Against Power Side-Channel AttacksNima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick, Akash Kumar. 1-6 [doi]
• A Parallel Tempering Processing Architecture with Multi-Spin Update for Fully-Connected Ising ModelsYang Zhang, Xiangrui Wang, Dong Jiang, Zhanhong Huang, Gaopeng Fan, Enyi Yao. 1-6 [doi]
• A Sound and Complete Algorithm to Identify Independent Variables in a Reactive System SpecificationJosu Oca, Montserrat Hermo, Alexander Bolotov. 1-2 [doi]
• Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAsHao Zhang, Mengying Zhao, Huichuan Zheng, Yuqing Xiong, Yuhao Zhang, Zhaoyan Shen. 1-6 [doi]