Table of Contents

• Co-DTC: Concentric Trench-Based Integrated Capacitors for Advanced Chiplet-Based PlatformsYousef Safari, Yushu Zhao, Boris Vaisband. 1-6 [doi]
• HMNTT: A Highly Efficient MDC-NTT Architecture for Privacy-preserving ApplicationsChangxu Liu, Danqing Tang, Jie Song, Hao Zhou, Shoumeng Yan, Fan Yang. 7-12 [doi]
• FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline TransceiverChaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang. 13-18 [doi]
• IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace ApplicationsAibin Yan, Chen Dong, Xing Guo, Jie Song, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. 19-24 [doi]
• PerFT-N: Low-overhead Permanent Fault-Tolerance Mechanism for Neural Processing UnitsHaojie Jian, Chao Chen, Zheng Wang, Pengfei Wu. 25-31 [doi]
• DETECTive: Machine Learning-driven Automatic Test Pattern Prediction for Faults in Digital CircuitsVincenzo Petrolo, Sourav Medya, Mariagrazia Graziano, Debjit Pal. 32-37 [doi]
• Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided LogicSeunggyu Lee, Wonjae Lee, Youngsoo Shin. 38-43 [doi]
• AltGraph: Redesigning Quantum Circuits Using Generative Graph Models for Efficient OptimizationCollin Beaudoin, Koustubh Phalak, Swaroop Ghosh. 44-49 [doi]
• CASH: Criticality-Aware Split Hybrid L1 Data CacheShruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, Sandeep Chandran. 50-56 [doi]
• A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of TransformersGian Singh, Sarma B. K. Vrudhula. 57-62 [doi]
• ML-Fusion: Determining Memory Levels for Data Reuse Between DNN LayersZikang Zhou, Xuyang Duan, Kaiqi Chen, Yaqi Chen, Jun Han 0003. 63-68 [doi]
• EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design AutomationPratik Shrestha, Alec Aversa, Saran Phatharodom, Ioannis Savidis. 69-77 [doi]
• SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS AttacksEbadollah Taheri, Pooya Aghanoury, Sudeep Pasricha, Mahdi Nikdast, Nader Sehatbakhsh. 78-85 [doi]
• TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined RadiosYichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini. 86-91 [doi]
• GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure SiliconPratyush Nandi, Anubhav Mishra, Madhav Rao. 92-97 [doi]
• DroneBandit: Multi-armed contextual bandits for collaborative edge-to-cloud inference in resource-constrained nanodronesGuillaume Chacun, Mehdi Akeddar, Thomas Rieder, Bruno Da Rocha Carvalho, Marina Zapater. 98-104 [doi]
• MARS: MAximizing throughput for MPPT-based self-sustaining LoRa SystemsRuben Dominguez, José Baca, Chen Pan. 105-110 [doi]
• Efficient Exploration in Edge-Friendly Hyperdimensional Reinforcement LearningYang Ni, William Youngwoo Chung, Samuel Cho, Zhuowen Zou, Mohsen Imani. 111-118 [doi]
• Q-Embroidery: A Study on Weaving Quantum Error Correction into the Fabric of Quantum ClassifiersAvimita Chatterjee, Debarshi Kundu, Swaroop Ghosh. 119-124 [doi]
• A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number SystemWenhui Zhang, Xinkuang Geng, Qin Wang, Jie Han 0001, Honglan Jiang. 125-131 [doi]
• Application of Quantum Tensor Networks for Protein ClassificationDebarshi Kundu, Archisman Ghosh, Srinivasan Ekambaram, Jian Wang 0094, Nikolay V. Dokholyan, Swaroop Ghosh. 132-137 [doi]
• Energy Efficient Multi-Modal Stress Detection System with Dynamic Adaptive Spiking NeuronsPhani Pavan Kambhampati, Ajay B. S, Madhav Rao. 138-143 [doi]
• Communication Minimized Model-Architecture Co-design for Efficient Convolution AccelerationWendi Sun, Wenhao Sun, Yifan Wang, Yi Kang, Song Chen 0001. 144-150 [doi]
• Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary DataflowFabian Lesniak, Annina Gutermann, Tanja Harbaum, Jürgen Becker 0001. 151-157 [doi]
• Incremental SAT-based Exact SynthesisSunan Zou, Jiaxi Zhang 0001, Guojie Luo. 158-163 [doi]
• An Open-Source Fast Parallel Routing Approach for Commercial FPGAsXinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young. 164-169 [doi]
• Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine LearningYuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon. 170-176 [doi]
• Scalable Flip-Flop Clustering Using Divide and Conquer For Capacitated K-MeansAndrew B. Kahng, Sayak Kundu, Shreyas Thumathy. 177-184 [doi]
• Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural AttacksArmin Darjani, Nima Kavand, Akash Kumar 0001. 185-191 [doi]
• The Fuzz Odyssey: A Survey on Hardware Fuzzing Frameworks for Hardware Design VerificationRaghul Saravanan, Sai Manoj Pudukotai Dinakarrao. 192-197 [doi]
• On Hardware Trojan Detection using Oracle-Guided Circuit LearningRajesh Kumar Datta, Guangwei Zhao, Dipali Jain, Kaveh Shamsi. 198-203 [doi]
• DM-TEE: Trusted Execution Environment for Disaggregated MemoryKe Xia, Sheng Wei 0001. 204-209 [doi]
• LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENCPengzhou He, Ben Mongirdas, Çetin Kaya Koç, Jiafeng Xie. 210-215 [doi]
• Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMsPrasanna Ravi, Shivam Bhasin, Anupam Chattopadhyay, Aikata, Sujoy Sinha Roy. 216-221 [doi]
• Exploring Generalization of Shoup Modular MultiplierOleg Mazonka, Mohammed Nabeel Thari Moopan, Michail Maniatakos. 222-227 [doi]
• Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-DesignSuraj Mandal, Debapriya Basu Roy. 228-232 [doi]
• Assert-O: Context-based Assertion Optimization using LLMsSamit Shahnawaz Miftah, Amisha Srivastava, Hyunmin Kim, Kanad Basu. 233-239 [doi]
• Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive AnalysisRaghul Saravanan, Sai Manoj Pudukotai Dinakarrao. 240-245 [doi]
• Harnessing Heterogeneity for Targeted Attacks on 3-D ICsAlec Aversa, Ioannis Savidis. 246-251 [doi]
• Navigating SoC Security Landscape on LLM-Guided PathsSudipta Paria, Aritra Dasgupta, Swarup Bhunia. 252-257 [doi]
• A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital SignatureGaoming Du, Zhuo Chen, Zhenmin Li, Xiaolei Wang, Duoli Zhang. 258-262 [doi]
• Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)Omid Bazgir, Satwik Gali, Tooraj Nikoubin. 263-267 [doi]
• A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC OperationsDhandeep Challagundla, Ignatius Bezzam, Riadul Islam. 268-271 [doi]
• Highly Efficient Load-Balanced Dataflow for SpGEMMs on Systolic ArraysGuocheng Zhao, Yongxiang Cao. 272-276 [doi]
• A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling OperationZihan Yin, Annewsha Datta, Shwetha Vijayakumar, Ajey P. Jacob, Akhilesh Jaiswal 0001. 277-281 [doi]
• An Analytical Model for High-Frequency Through Silicon ViasMohamed Adel Gharib, Salma Abdelzaher, Inna Partin-Vaisband. 282-286 [doi]
• Generalizable and Relation Sensitive Netlist Representation for Analog Circuit DesignSurya Penmetsa, Fahad Rahman Amik, Zhanguang Zhang, Yingying Fu, Yingxue Zhang, Wulong Liu, Jianye Hao. 287-291 [doi]
• Integrated MAC-based Systolic Arrays: Design and Performance EvaluationDantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao. 292-295 [doi]
• Improving Block Management in 3D NAND Flash SSDs with Sub-Block First Write SequencingMatchima Buddhanoy, Kamil Khan, Aleksandar Milenkovic, Sudeep Pasricha, Biswajit Ray. 296-300 [doi]
• Cost-Effective Value Predictor for ILP processors through Design Space ExplorationLing Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu. 301-304 [doi]
• Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAsHariprasadh Govindasamy, Babak Esfandiari, Paulo Garcia. 305-309 [doi]
• FedTR: Federated Learning Framework with Transfer Learning for Industrial Visual InspectionVikash Sathiamoorthy, Shuo Huai, Hao Kong, Di Liu 0002, Wendy Yong Yi Loy, Christian Makaya, Daren Ho, Ravi Subramaniam, Qian Lin 0001, Weichen Liu. 310-314 [doi]
• Sparsifying Graph Neural Networks with Compressive SensingMohammed Alawad, Mohammad Munzurul Islam. 315-318 [doi]
• Advanced Continuous-Time Convolution Framework for Security Assurance in Wireless Sensor NetworksMohammad Mezanur Rahman Monjur, Qiaoyan Yu. 319-322 [doi]
• Autotile: Autonomous Task-tiling for Deep Inference on Battery-less Embedded SystemJishnu Banerjee, Sahidul Islam, Wei Wei, Chen Pan, Mimi Xie. 323-327 [doi]
• Soft Error Resilience Analysis of LSTM NetworksChristopher P. Vasquez, Travis LeCompte, Xu Yuan, Nian-Feng Tzeng, Lu Peng. 328-332 [doi]
• Comprehensive Analysis of Generated Single Event Transients in Most Common Logic Cells of Skywater's 130-nm TechnologyJanani Aravind, Victor Oyadongha, Daniel B. Limbrick. 333-337 [doi]
• HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processorsJingzhou Li, Huaiyu Chen, Wenbin Zhang, Hu He. 338-342 [doi]
• Educational Tool-spaces for Convolutional Neural Network FPGA Design Space Exploration Using High-Level SynthesisRichard C. Yarnell, Mousam Hossain, Raul Graterol, Ayush Pindoria, Sujan Ghimire, Muhtasim Alam Chowdhury, Soheil Salehi, Yu Bai 0004, Ronald F. DeMara. 343-346 [doi]
• Step-by-Step Tutoring Support for Student Success in Circuit Analysis CoursesBrian J. Skromme, Megan A. O'Donnell, Wendy M. Barnard. 347-350 [doi]
• System Architecture Optimization for Vertical Power DeliverySriharini Krishnakumar, Yaroslav Popryho, Inna Partin-Vaisband. 351-352 [doi]
• GeckOpt: LLM System Efficiency via Intent-Based Tool SelectionMichael Fore, Simranjit Singh 0003, Dimitrios Stamoulis. 353-354 [doi]
• Word2HyperVec: From Word Embeddings to Hypervectors for Hyperdimensional ComputingAlaaddin Goktug Ayar, Sercan Aygun, M. Hassan Najafi, Martin Margala. 355-356 [doi]
• VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet NetworksDuo Yu, Ang Li, Naifeng Jing, Jianfei Jiang 0001, Weiguang Sheng, Qin Wang 0009. 357-363 [doi]
• TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based AcceleratorXinyi Li, Wenjie Fan 0004, Heng Zhang, Jinlun Ji, Tong Cheng, Shiping Li, Li Li, Yuxiang Fu. 364-369 [doi]
• An Embedded Multi-Layer Spiral Square Inductor for Integrated Power Delivery - Physical Design and Analytical ModelsRami Rasheedi, Inna Partin-Vaisband. 370-375 [doi]
• On Advanced Methodologies for Microarchitecture Design Space ExplorationTianji Liu, Qijing Wang, Lixin Liu, Fangzhou Wang, Evangeline F. Y. Young. 376-382 [doi]
• A Multi-agent Generative Model for Collaborative Global Routing RefinementQijing Wang, Jinwei Liu, Martin D. F. Wong, Evangeline F. Y. Young. 383-389 [doi]
• A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR DropAndrew B. Kahng, Bodhisatta Pramanik, Mingyu Woo. 390-396 [doi]
• A Bounding Box-based Net Partitioning Method for Double-sided RoutingFang-Yu Hsu, Tzu-Chuan Lin, Wai-Kei Mak, Ting-Chi Wang. 397-402 [doi]
• An Electromigration-Aware Wire Sizing Methodology via Particle Swarm OptimizationOlympia Axelou, Kostas Kolomvatsos, George Floros 0002, Nestor E. Evmorfopoulos, Georg I. Georgakos, George Stamoulis. 403-408 [doi]
• EPIC: Efficient and Proactive Instruction-level CyberdefensePreet Derasari, Guru Venkataramani. 409-414 [doi]
• Boolean Domain Attack on Corrupt and Correct Based Logic Locking TechniquesJoseph Madera, Kyle Juretus. 415-420 [doi]
• SSFuzz: Generating syntactic and semantic seeds for RISC-V processorsShaoqian Jin, Yulin Li, Liwei Chen, Gang Shi. 421-426 [doi]
• Accelerating Homomorphic Comparison Operations for Thresholding Using an Asymmetric Input Range and Input ScalingSunwoong Kim, Wonhee Cho 0001. 427-432 [doi]
• Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and RoutingXinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F. Y. Young, Martin D. F. Wong. 433-439 [doi]
• Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM DesignsShan Shen, Dingcheng Yang, Yuyang Xie, Chunyan Pei, Bei Yu 0001, Wenjian Yu. 440-445 [doi]
• Feature Fusion based Hotspot Detection with R-EfficientNetChun Wang, Yi Fang, Sihai Zhang. 446-451 [doi]
• PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution SmoothingFeng Guo, Jiawei Liu, Jianwang Zhai, Jingyu Jia, Kang Zhao, Chuan Shi. 452-458 [doi]
• Using EM Side-Channels Near a Bluetooth Server Implementation to Monitor Bit-Level Leakages in BLE Communication ChannelsVishnuvardhan Venkatramani Iyer, Jacob D. Rezac. 459-464 [doi]
• DTjRTL: A Configurable Framework for Automated Hardware Trojan Insertion at RTLRuochen Dai, Zhaoxiang Liu, Orlando Arias, Xiaolong Guo, Tuba Yavuz. 465-470 [doi]
• DyFORA: Dynamic Firmware Obfuscation and Remote Attestation using Hardware SignaturesSajeed Mohammad, Farimah Farahmandi. 471-476 [doi]
• Comprehensive Analysis of Consistency and Robustness of Machine Learning Models in Malware DetectionSreenitha Kasarapu, Dipkamal Bhusal, Nidhi Rastogi, Sai Manoj Pudukotai Dinakarrao. 477-482 [doi]
• Blockchain-Enabled Whitelisting Mechanisms for Enhancing Security in 3D ICsGaines Odom, Hardhik Mohanty, Ujjwal Guin, Bhaskar Krishnamachari. 483-488 [doi]
• SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented EstimationBulbul Ahmed, M. Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor. 489-494 [doi]
• Extended Abstract: Pre-Silicon Vulnerability Assessment for AI/ML HardwareFurkan Aydin, Emre Karabulut, Aydin Aysu. 495 [doi]
• Evolutionary Large Language Models for Hardware Security: A Comparative SurveyMohammad Akyash, Hadi Mardani Kamali. 496-501 [doi]
• Exploring the Potential of Decision Diagrams for Efficient In-Memory Design VerificationKhushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan 0002, Rolf Drechsler. 502-506 [doi]
• Anomaly Detection Method based on Discrete Particle Swarm Optimization for Continuous-Flow Microfluidic BiochipsYangjie Wu, Yuhan Zhu, Genggeng Liu, Xing Huang. 507-510 [doi]
• ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern GenerationQijing Wang, Xiaopeng Zhang 0009, Martin D. F. Wong, Evangeline F. Y. Young. 511-515 [doi]
• IR drop Prediction Based on Machine Learning and Pattern ReductionYong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, Chun-Yao Wang. 516-519 [doi]
• An Automatic Insertion Scheme of Extra Via for DSA-MP Hybrid LithographyYuqin Wang, Cheng Guo, Xiaojing Su, Xin Hong, Zixi Liu, Xiaohuan Ling, Bojie Ma, Pengyu Ren, Yujie Jiang, Yajuan Su, Yayi Wei. 520-524 [doi]
• A P&R Co- Optimization Engine for Reducing CongestionDongliang Xia, Wenxin Yu, Zhaoqi Fu, Zejun Gan, Chengjin Li, Yupeng Zhang. 525-528 [doi]
• Washing Optimization Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array BiochipsJunqian Huang, Yuhan Zhu, Xing Huang, Genggeng Liu. 529-532 [doi]
• Error Recovery Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array BiochipsZhenyuan Wu, Yuhan Zhu, Xing Huang, Genggeng Liu. 533-536 [doi]
• MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM AcceleratorsJinyu Bai, He Zhang, Wang Kang 0001. 537-540 [doi]
• AFeCAM: An Energy Efficient Analog 1FeFET Content Addressable MemorySabrina Hassan Moon, Dayane Reis. 541-545 [doi]
• A New Routing Strategy to Improve Success Rates of Quantum ComputersFang Qi, Xin Fu, Xu Yuan 0001, Nian-Feng Tzeng, Lu Peng 0001. 546-550 [doi]
• RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager SecuritySepehr Tabrizchi, Nedasadat Taheri, Shaahin Angizi, Arman Roohi. 551-555 [doi]
• Evaluating Efficacy of Model Stealing Attacks and Defenses on Quantum Neural NetworksSatwik Kundu, Debarshi Kundu, Swaroop Ghosh. 556-559 [doi]
• SNAC: Mitigation of Snoop-Based Attacks with Multi-Tier Security in NoC ArchitecturesSiqin Liu, Saumya Chauhan, Avinash Karanth. 560-563 [doi]
• Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence AttackTasnuva Farheen, Sourav Roy, Andrew Cannon, Jia Di, Shahin Tajik, Domenic Forte. 564-568 [doi]
• Detecting Hardware Trojans using Model Guided Symbolic ExecutionRuochen Dai, Tuba Yavuz. 569-573 [doi]
• Breaching the Gap: Modelling SRAM-PUFs via Side-Channel SignaturesKuheli Pratihar, Soumi Chatterjee, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay. 574-578 [doi]
• Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion AbilityGwok-Waa Wan, Sam-Zaak Wong, Xi Wang. 579-582 [doi]
• LDL-SCA: Linearized Deep Learning Side-Channel Attack Targeting Multi-tenant FPGAs✱Yankun Zhu, Siting Liu 0001, Liyu Yang, Pingqiang Zhou. 583-587 [doi]
• LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit TransformationsRasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, Swarup Bhunia. 588-591 [doi]
• Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design StageZixi Liu, Yibo Lin, Xiaojing Su, Xiaohuan Ling, Xin Hong, Bojie Ma, Yajuan Su, Yayi Wei. 592-598 [doi]
• Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention FusionYunji Qin, Wenqi Lou, Chao Wang, Lei Gong, Xuehai Zhou. 599-603 [doi]
• Performance Analysis of OFA-NAS ResNet Topologies Across Diverse Hardware Compute UnitsPrashanth H. C., Madhav Rao. 604-607 [doi]
• Transductive Spiking Graph Neural Networks for LoihiShay Snyder, Victoria Clerico, Guojing Cong, Shruti R. Kulkarni, Catherine D. Schuman, Sumedh R. Risbud, Maryam Parsa. 608-613 [doi]
• Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning AccelerationBokyung Kim, Hai Li, Yiran Chen 0001. 614-619 [doi]
• IRET: Incremental Resolution Enhancing TransformerBanafsheh Saber Latibari, Soheil Salehi, Houman Homayoun, Avesta Sasan. 620-625 [doi]
• FFCL: Forward-Forward Net with Cortical Loops, Training and Inference on Edge Without BackpropogationAli Karkehabadi, Houman Homayoun, Avesta Sasan. 626-632 [doi]
• Energy Harvesting-assisted Ultra-Low-Power Processing-in-Memory Accelerator for ML ApplicationsSanket Shukla, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao. 633-638 [doi]
• Fortified-Edge 4.0: A ML-Based Error Correction Framework for Secure Authentication in Collaborative Edge ComputingSeema G. Aarella, Venkata Prasanth Yanambaka, Saraju P. Mohanty, Elias Kougianos. 639-644 [doi]
• PositCL: Compact Continual Learning with Posit Aware QuantizationVedant Karia, Abdullah M. Zyarah, Dhireesha Kudithipudi. 645-650 [doi]
• Ultra-Area-Efficient Cryogenic XNOR Logic Gate with Superconducting Heater Cryotron to Advance High-Performance ComputingShamiul Alam, Ahmedullah Aziz. 651-656 [doi]
• ToEFL: A Novel Approach for Training on Edge in Smart AgricultureAlakananda Mitra, Saraju P. Mohanty, Elias Kougianos. 657-662 [doi]
• Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman FilterSiamak Biglari, Ruixiao Huang, Hui Zhao 0013, Saraju P. Mohanty. 663-668 [doi]
• Security-by-Design For Smart ElectronicsVenkata Prasanth Yanambaka, Ayas Kanta Swain, Saswat Kumar Ram, Saraju P. Mohanty. 669 [doi]
• PACAC: PYNQ Accelerated Cardiac Arrhythmia Classifier with secure transmission- A Deep Learning based ApproachSoumyashree Mangaraj, Jaganath Prasad Mohanty, Samit Ari, Ayas Kanta Swain, Kamalakanta Mahapatra. 670-675 [doi]
• PUFshield: A Hardware-Assisted Approach for Deepfake Mitigation Through PUF-Based Facial Feature AttestationVenkata Karthik Vishnu Vardhan Bathalapalli, Venkata Prasanth Yanambaka, Saraju P. Mohanty, Elias Kougianos. 676-681 [doi]
• Modular Security Evaluation Platform for Physiological Closed-Loop Control SystemsSamir Ahmed, Shakil Mahmud, Robert Karam. 682-687 [doi]
• Hardware Accelerated Quantized Hand Written Digit Recognition via High Level SynthesisPawan Oraon, Soumyashree Mangaraj, Ayas Kanta Swain, Kamalakanta Mahapatra. 688-693 [doi]
• Resource-Aware Saliency-Guided Differentiable Pruning for Deep Neural NetworksUttej Kallakuri, Edward Humes, Tinoosh Mohsenin. 694-699 [doi]
• KDTree-SOM: Self-organizing Map based Anomaly Detection for Lightweight Autonomous Embedded SystemsPing-Xiang Chen, Dongjoo Seo, Biswadip Maity, Nikil D. Dutt. 700-705 [doi]
• A Cryptographic Hardware Engineering Course based on FPGA and Security Analysis EquipmentZhaojun Lu, Qidong Chen, Peng Xu, Jiliang Zhang 0002, Gang Qu 0001. 706-711 [doi]
• Feature-driven Approximate Computing for Wearable Health-Monitoring SystemsNishanth Goud Chennagouni, Mashrafi Alam Kajol, Diliang Chen, Dongpeng Xu 0001, Qiaoyan Yu. 712-717 [doi]
• Can Stochastic Computing Truly Tolerate Bit Flips?Yutong Wang, Zhaojun Ni, Siting Liu 0001. 718-723 [doi]
• Probabilistic Bayesian Neural Networks for Efficient InferenceMohammed Alawad, Md Ishak. 724-729 [doi]
• NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point ConvolutionsArash Fayyazi, Mahdi Nazemi, Arya Fayyazi, Massoud Pedram. 730-735 [doi]
• HSCONN: Hardware-Software Co-Optimization of Self-Attention Neural Networks for Large Language ModelsSiqin Liu, Prakash Chand Kuve, Avinash Karanth. 736-741 [doi]
• A Remote FPGA-based Experimental Teaching System Design Supporting Single-board Multi-user and Multi-board Single-user Operations in MOOCsZhixiong Di, Xufeng Wei, Yiduo Chen, Shuanglong Wu, Peihao Sun, Qiang Wu. 742-747 [doi]
• Toward Fair Ultrasound Computing Tomography: Challenges, Solutions and OutlookYi-sheng, Junhuan Yang, Youzuo Lin, Weiwen Jiang, Lei Yang. 748-753 [doi]
• Enhanced AI for Science using Diffusion-based Generative AI - A Case Study on Ultrasound Computing TomographyJunhuan Yang, Yi-sheng, Yuzhou Zhang, Hanchen Wang, Youzuo Lin, Lei Yang. 754-759 [doi]
• A Deep Multimodal Representation Learning Framework for Accurate Molecular Properties PredictionYuxin Yang, Zixu Wang, Pegah Ahadian, Abby Jerger, Jeremy Zucker, Song Feng, Feixiong Cheng, Qiang Guan. 760-765 [doi]
• P-ReTI: Silicon Photonic Accelerator for Greener and Real-Time AIDharanidhar Dang, Priyabrata Dash, Ahmedullah Aziz. 766-769 [doi]
• Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on ComputingDeniz Najafi, Sepehr Tabrizchi, Ranyang Zhou, Mohammadreza Amel Solouki, Andrew Marshall, Arman Roohi, Shaahin Angizi. 770-775 [doi]
• Asynchronous Neuromorphic Optimization in LavaShay Snyder, Sumedh R. Risbud, Maryam Parsa. 776-778 [doi]
• Event-Driven Sensing and Embedded Neuromorphic Platforms for Gamma Radiation MonitoringBrett Witherspoon, Aaron R. Young. 779-784 [doi]
• Review of Neuromorphic Processing for Vision SensorsMst Shamim Ara Shawkat, Shante Hicks, Nahin Irfan. 785-790 [doi]