Table of Contents

• SafeDE: a flexible Diversity Enforcement hardware module for light-locksteppingFrancisco Bas, Sergi Alcaide, Ruben Lorenzo, Guillem Cabo, Guillermo Gil, Oriol Sala, Fabio Mazzocchetti, David Trilla, Jaume Abella 0001. 1-7 [doi]
• Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital SystemsTiziano Fiorucci, Jean-Marc Daveau, Giorgio Di Natale, Philippe Roche. 1-6 [doi]
• Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level NetlistsKento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa. 1-4 [doi]
• A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire DelayYukiya Miura, Shingo Tsutsumi. 1-6 [doi]
• Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random ForestsTatsuki Kurihara, Nozomu Togawa. 1-4 [doi]
• TAURUM P2T: Advanced Secure CAN-FD Architecture for Road VehicleFranco Oberti, Ernesto Sánchez 0001, Alessandro Savino, Filippo Parisi, Stefano Di Carlo. 1-7 [doi]
• Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State ChecksumsSuvadeep Banerjee, Abhijit Chatterjee. 1-7 [doi]
• SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing ValidationOriol Sala, Sergi Alcaide, Guillem Cabo, Francisco Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Guillermo Gil, Fabio Mazzocchetti, Jaume Abella 0001. 1-7 [doi]
• An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTMKazunari Takasaki, Ryoichi Kida, Nozomu Togawa. 1-7 [doi]
• Flip Flop Weighting: A technique for estimation of safety metrics in Automotive DesignsFelipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer 0001. 1-7 [doi]
• Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer FrameworkMitko Veleski, Michael Hübner 0001, Milos Krstic, Rolf Kraemer. 1-7 [doi]
• Addressing Soft Error and Security Threats in DNNs Using Learning Driven Algorithmic ChecksChandramouli N. Amarnath, Md Imran Momtaz, Abhijit Chatterjee. 1-4 [doi]
• MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN AcceleratorsStéphane Burel, Adrian Evans, Lorena Anghel. 1-6 [doi]
• CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation ModelsKensuke Murakami, Mahfuzul Islam, Hidetoshi Onodera. 1-6 [doi]
• Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate ComputingBastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard 0001. 1-7 [doi]
• Concurrent Test of Reconfigurable Scan Networks for Self-Aware SystemsChih-Hao Wang, Natalia Lylina, Ahmed Atteya, Tong-Yu Hsieh, Hans-Joachim Wunderlich. 1-7 [doi]
• Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition MethodShuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi 0001. 1-6 [doi]
• Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box FuzzingKazuki Yoshisue, Yutaka Masuda, Tohru Ishihara. 1-7 [doi]
• A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded DevicesAnnachiara Ruospo, Davide Piumatti, Andrea Floridia, Ernesto Sánchez 0001. 1-6 [doi]
• A Memristive Architecture for Process Variation Aware Gas Sensing and Logic OperationsSaurabh Khandelwal, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir. 1-4 [doi]
• Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage ImprovementRiccardo Cantoro, Patrick Girard 0001, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel. 1-4 [doi]
• Unsupervised Recycled FPGA Detection Based on Direct Density Ratio EstimationYuya Isaka, Foisal Ahmed, Michihiro Shintani, Michiko Inoue. 1-6 [doi]
• System-Level Test: State of the Art and ChallengesDavide Appello, H. H. Chen, Matthias Sauer 0002, Ilia Polian, Paolo Bernardi, Matteo Sonza Reorda. 1-7 [doi]
• Adaptive-HMD: Accurate and Cost-Efficient Machine Learning-Driven Malware Detection using Microarchitectural EventsYifeng Gao, Hosein Mohammadi Makrani, Mehrdad Aliasgari, Amin Rezaei, Jessica Lin 0001, Houman Homayoun, Hossein Sayadi. 1-7 [doi]
• Neuron-PUF: Physical Unclonable Function Based on a Single Spiking NeuronMohamed Elshamy, Haralampos-G. Stratigopoulos. 1-6 [doi]
• FPGA Checkpointing for Scientific ComputingMarc Perelló Bacardit, Leonardo Bautista-Gomez, Osman S. Unsal. 1-7 [doi]
• EnSuRe: Energy & Accuracy Aware Fault-tolerant Scheduling on Real-time Heterogeneous SystemsSangeet Saha, Adewale Adetomi, Xiaojun Zhai, Server Kasap, Shoaib Ehsan, Tughrul Arslan, Klaus D. McDonald-Maier. 1-4 [doi]
• A New Domains-based Isolation Design Flow for Reconfigurable SoCsAndrea Portaluri, Corrado De Sio, Sarah Azimi, Luca Sterpone. 1-7 [doi]
• Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective HardeningJosie E. Rodriguez Condia, Paolo Rech, Fernando Fernandes dos Santos, Luigi Carro, Matteo Sonza Reorda. 1-7 [doi]
• Robust Adaptive Read Scheme for 7nm Configuration SRAMsSree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Pulipati, Joy Chen, Teja Masina. 1-4 [doi]
• Integrating an Interconnect BIST with Crosstalk Avoidance HardwareMahsa Akhsham, Zainalabedin Navabi. 1-6 [doi]
• High-level Intellectual Property Obfuscation via Decoy ConstantsLevent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini. 1-7 [doi]