Abstract is missing.
- Foreword: ATS 2022Jin-Fu Li, Jing-Jia Liou. [doi]
- A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent StorageAibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. 1-6 [doi]
- Locating Critical-Reliability Gates for Sequential Circuits based on the Time Window Graph ModelWeidong Zhu, Jianhui Jiang, Zhanhui Shi. 7-12 [doi]
- Fault Securing Techniques for Yield and Reliability Enhancement of RRAMShyue-Kung Lu, Zhi-Jia Liu, Masaki Hashizume. 13-18 [doi]
- An obfuscation scheme of scan chain to protect the cryptographic chipsHuixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui. 19-24 [doi]
- An Authentication-Based Secure IJTAG NetworkShih-Chun Yeh, Kuen-Jong Lee, Dong-Yi Chen. 25-30 [doi]
- A New Access Protocol for Elevating the Security of IJTAG NetworkGaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat. 31-36 [doi]
- High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOSTKeno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001. 37-42 [doi]
- On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generatorsAnkush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragan. 43-48 [doi]
- Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation OscillatorsMasao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume. 49-53 [doi]
- Aging Impact of Power MOSFETs in Charger with Different Operation FrequencyKuan-Hsun Duh, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen, Ming-Yan Fan. 54-59 [doi]
- On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and PredictionTakaaki Kato, Yousuke Miyake, Seiji Kajihara. 60-65 [doi]
- Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic ReconfigurationYu-You Chou, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen. 66-71 [doi]
- Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing TestUtsav Jana, Sourav Banerjee, Binod Kumar 0001, Madhu B, Shankar Umapathi, Masahiro Fujita. 72-77 [doi]
- Online Periodic Test of Reconfigurable Scan NetworksNatalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich. 78-83 [doi]
- Using Formal Methods to Support the Development of STLs for GPUsNikolaos Ioannis Deligiannis, Tobias Faller, Josie E. Rodriguez Condia, Riccardo Cantoro, Bernd Becker 0001, Matteo Sonza Reorda. 84-89 [doi]
- Intrusion Detection and Obfuscation Mechanism for PUF-Based AuthenticationSying-Jyan Wang, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong. 90-95 [doi]
- PointerChecker: Tag-Based and Hardware-Assisted Memory Safety against Memory CorruptionXiaofan Nie, Liwei Chen, Gang Shi. 96-101 [doi]
- Using Hopfield Networks to Correct Instruction FaultsTroya Çagil Köylü, Moritz Fieback, Said Hamdioui, Mottaqiallah Taouil. 102-107 [doi]
- Two-Dimensional Test Generation ObjectiveIrith Pomeranz. 108-113 [doi]
- Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered LinesIrith Pomeranz. 114-119 [doi]
- Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate FaultsHari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman. 120-125 [doi]
- Hybrid Rule-based and Machine Learning System for Assertion Generation from Natural Language SpecificationsAditi, Michael S. Hsiao. 126-131 [doi]
- AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network AcceleratorsWan Ju Huang, Hsiao-Wen Fu, Tsung-Chu Huang. 132-137 [doi]
- A Hardware Trojan Trigger Localization Method in RTL based on Control Flow FeaturesHao Huang, Haihua Shen, Shan Li, Huawei Li. 138-143 [doi]
- FPGA-Based Emulation for Accelerating Transient Fault Reduction AnalysisZih-Ming Huang, Dun-An Yang, Jing-Jia Liou, Harry H. Chen. 144-149 [doi]
- On No-Reference Error Detection of an Image Stitching System Based on Error-ToleranceTong-Yu Hsieh, Pao-Wei Tsui, Jun-Tsung Wu. 150-155 [doi]
- Usable Circuits with Imperfect Scan LogicIrith Pomeranz. 156-161 [doi]