Table of Contents

• Structured DFT Development Approach for Chisel-Based High Performance RISC-V ProcessorsBin Zhang, Ye Cai, Zhiheng He, Sen Liang, Wei He. 1-6 [doi]
• Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash MemoryShyue-Kung Lu, Xin Dong. 1-6 [doi]
• Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMsMeng-Shan Wu, Yen-Lin Chua, Jin-Fu Li 0001, Yun-Ting Chuan, Shih-Hsu Huang. 1-6 [doi]
• A Low Overhead and Double-Node-Upset Self-Recoverable LatchAibin Yan, Fan Xia, Tianming Ni, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. 1-5 [doi]
• Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation HardnessAibin Yan, Chao Zhou, Shaojie Wei, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. 1-6 [doi]
• A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA ImplementationKentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi 0001, Keno Sato, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa. 1-6 [doi]
• Hunting for Hardware Trojan in Gate Netlist: A Stacking Ensemble Learning PerspectiveLiang Hong, Ge Zhu, Jing Zhou, Xuefei Li, Ziyi Chen, Wei Hu. 1-6 [doi]
• Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust ApplicationsAnwesh Kumar Samal, Sandeep Kumar, Atin Mukherjee. 1-5 [doi]
• Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOSHao-Chiao Hong, Chien-Hung Chen, Yu-Wun Chen. 1-5 [doi]
• Silicon Lifecycle Management: Trends, Challenges and Solutions : Tutorial 2Yervant Zorian. 1 [doi]
• Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based CalibrationYi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang. 1-6 [doi]
• Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4Wei-Ji Chao, Tong-Yu Hsieh. 1-6 [doi]
• Scalable hierarchical DFT technologies for AI, SOC and multi-die : Tutorial 1Lee Harrison, Wu Yang. 1 [doi]
• Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning TechniqueAyano Takaya, Michihiro Shintani. 1-6 [doi]
• Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and EfficiencyPo-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen. 1-6 [doi]
• Toward Improvement and Evaluation of Reconstruction Capability of CapsNet-Based Wafer Map Defect Pattern ClassifierYuki Yamanaka, Masayuki Arai, Yoshikazu Nagamura, Satoshi Fukumoto. 1-6 [doi]
• Optimizing Post-Silicon Validation for FPGA Serial Configuration using an Automation Framework and Timing Characterization VerificationMohd Amiruddin Zainol, Sompon Khamron, Ng Gua Bin. 1-6 [doi]
• Test industry challenges and solutions as observed by the leading physical implementation solution provider : Invited Talk 2Janet Olson. 1 [doi]
• Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress TestChen-Lin Tsai, Shi-Yu Huang. 1-6 [doi]
• Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz TestDavid C. Keezer, Dany Minier, Hongjie Li. 1-6 [doi]
• On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable FaultsShogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume. 1-6 [doi]
• Semiconductor Packaging Revolution in the Era of Chiplets : Keynote 1Yasumitsu Orii. 1 [doi]
• Technology for The Future of Computing : Keynote 2Shintaro Yamamichi. 1 [doi]
• Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical ApplicationsAibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. 1-6 [doi]
• Moore Meets Murphy : Invited Talk 1Erik Jan Marinissen. 1 [doi]
• BDD-Based Self-Test Program Generation for Processor CoresHao Cheng, Chi-Jhe Li, Hung-Lin Chen, Jiun-Lang Huang. 1-6 [doi]
• Software Defect Detection Based on Feature Fusion and Alias AnalysisXuejian Li, Zhengguang Zhu. 1-6 [doi]