Table of Contents

• Integrated Soft Error Resilience and Self-TestErol Koser, Sebastian Krosche, Walter Stechele. 1-6 [doi]
• An adaptive energy-efficient task scheduling under execution time variation based on statistical analysisTakashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu. 1-7 [doi]
• Redesigning software and systems for non-volatile processors on self-powered devicesMengying Zhao, Keni Qiu, Yuan Xie, Jingtong Hu, Chun Jason Xue. 1-6 [doi]
• Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuitsValerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino. 1-6 [doi]
• Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variationMaede Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. 1-6 [doi]
• Restricting writes for energy-efficient hybrid cache in multi-core architecturesSukarn Agarwal, Hemangee K. Kapoor. 1-6 [doi]
• Power and energy reduction of racetrack-based caches by exploiting shared shift operationsSeyed Saber Nabavi Larimi, Mehdi Kamal, Ali Afzali-Kusha, Hamid Mahmoodi. 1-6 [doi]
• Automatic protocol configuration in single-channel low-power dynamic signaling for IoT devicesShahzad Muzaffar, Numan Saeed, Ibrahim M. Elfadel. 1-6 [doi]
• Synthesis on switching lattices of Dimension-reducible Boolean functionsAnna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco. 1-6 [doi]
• An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHzAbhiram Reddy Gundla, Tom Chen. 1-5 [doi]
• ForewordJaan Raik, Ian O'Connor, Thomas Hollstein, Krishnendu Chakrabarty. 1 [doi]
• Frequency domain characterization of batteries for the design of energy storage subsystemsYukai Chen, Enrico Macii, Massimo Poncino. 1-6 [doi]
• Power-efficient and slew-aware three dimensional gated clock tree synthesisMinghao Lin, Heming Sun, Shinji Kimura. 1-6 [doi]
• Power and area efficient clock stretching and critical path reshaping for error resilienceMini Jayakrishnan, Alan Chang, Tae-Hyoung Kim. 1-6 [doi]
• Faster-than-at-speed execution of functional programs: An experimental analysisPaolo Bernardi, Alberto Bosio, Giorgio Di Natale, A. Guerriero, F. Venini. 1-6 [doi]
• Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMOSyed Mohsin Abbas, Chi-Ying Tsui. 1-5 [doi]
• An FPGA-based testing platform for the validation of automotive powertrain ECUBoyang Du, Luca Sterpone. 1-7 [doi]
• Automatically comparing analog behavior using Earth Mover's DistanceAlexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker. 1-8 [doi]
• Conclusively verifying clock-domain crossings in very large hardware designsGuillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione. 1-6 [doi]
• Opportunistic circuit-switching for energy efficient on-chip networksYuan He 0002, Masaaki Kondo. 1-6 [doi]
• Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architecturesXueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan. 1-6 [doi]
• Power-aware test optimization for core-based 3D-SOCs under TSV-constraintsSabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya. 1-6 [doi]
• SoC oriented real-time high-quality stereo vision systemYanzhe Li, Kai Huang, Luc Claesen. 1-6 [doi]
• Design of a multi-style and multi-frequency FPGAJotham Vaddaboina Manoranjan, Solomon Surya Tej Mano Sajjan, Vivek B. Gujari, Kenneth S. Stevens. 1-6 [doi]
• Enabling in-memory computation of binary BLAS using ReRAM crossbar arraysDebjyoti Bhattacharjee, Farhad Merchant, Anupam Chattopadhyay. 1-6 [doi]
• Design of nonvolatile processors and applicationsFang Su, Zhibo Wang, Jinyang Li, Meng-Fan Chang, Yongpan Liu. 1-6 [doi]
• Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCsValentino Peluso, Andrea Calimera, Enrico Macii, Massimo Aliotoy. 1-6 [doi]
• Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generatorsWolfgang Ecker, Johannes Schreiner. 1-6 [doi]
• A low-power analog front-end neural acquisition design for seizure detectionMohammad Tohidi, Jens Kargaard Madsen, Martijn J. R. Heck, Farshad Moradi. 1-6 [doi]
• A compact, ultra-low power AES-CCM IP core for wireless body area networksVan-Phuc Hoang, Thi-Thanh-Dung Phan, Van-Lan Dao, Cong-Kha Pham. 1-4 [doi]
• XbarGen: A memristor based boolean logic synthesis toolMarcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio. 1-6 [doi]
• A Hybrid Power Estimation Technique to improve IP power models qualityAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier. 1-6 [doi]
• A novel soft error tolerant FPGA architectureMotoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi. 1-6 [doi]
• Efficient handling of the fault space in functional safety analysis utilizing formal methodsAlessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann. 1-7 [doi]
• Logic design with unipolar memristorsElad Amrani, Avishay Drori, Shahar Kvatinsky. 1-5 [doi]
• Online digital compensation Method for AMR sensorsAndreina Zambrano, Hans G. Kerkhoff. 1-6 [doi]
• A passive equalizer and its design methodology for global interconnects in VLSIsMoritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara. 1-6 [doi]
• Static energy reduction by performance linked dynamic cache resizingShounak Chakraborty, Hemangee K. Kapoor. 1-6 [doi]
• Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICsYi Zhao, S. Saqib Khursheed, Bashir M. Al-Hashimi, Zhiwen Zhao. 1-6 [doi]
• Comparative analysis of redundancy schemes for soft-error detection in low-cost space applicationsCharlotte Frenkel, Jean-Didier Legat, David Bol. 1-6 [doi]
• Optimistic clock adjustment for preventing Better-than-worst-case violationsSeyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi. 1-6 [doi]
• Stimuli generation through invariant mining for black-box verificationLuca Piccolboni, Graziano Pravadelli. 1-6 [doi]
• Speeding up safety verification by fault abstraction and simulation to transaction levelBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello. 1-6 [doi]
• Dynamic clock synchronization scheme between voltage domains in multi-core architectureJaehyun Kim, Kiyoung Choi, Sang-Heon Lee, Soojung Ryu. 1-6 [doi]
• Fast dynamic fault injection for virtual microcontroller platformsPeer Adelt, Bastian Koppelmann, Wolfgang Mueller, Markus Becker, Bernd Kleinjohann, Christoph Scheytt. 1-6 [doi]
• A VLSI architecture for real-time gradient guided image filteringLei Wu, Ching-Chuen Jong. 1-6 [doi]
• A 1.62 µW 8-channel ultra-high input impedance EEG amplifier for dry and non-contact biopotential recording applicationsMahshid Nasserian, Ali Peiravi, Farshad Moradi. 1-6 [doi]
• WCET overapproximation for software in the context of a Cyber-Physical SystemNiklas Krafczyk, Heinz Riener, Görschwin Fey. 1-6 [doi]
• The multi-channel small signal readout system for THz spectroscopy and imaging applicationsDariusz Obrebski, Cezary Kolacinski, Michal Zbiec, Przemyslaw Zagrajek. 1-6 [doi]