Table of Contents

• A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated CircuitsDaniel Adjei, Emmanuel Nti Darko, Degang Chen 0001. 1-5 [doi]
• Identifying Undetectable Defects Using Equivalence CheckingLars Hedrich, Inga Abel, Jaafar Mejri, Vladimir A. Zivkovic. 6-10 [doi]
• Unsupervised Learning Provides Intelligence for Testing Hard to Detect FaultsSoham Roy, Vishwani D. Agrawal. 11-15 [doi]
• Wafer2Spike: Spiking Neural Network for Wafer Map Pattern ClassificationAbhishek Kumar Mishra, Suman Kumar, Anush Niranjan Lingamoorthy, Anup Das 0001, Nagarajan Kandasamy. 16-20 [doi]
• From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at IntelBrian Pajak, Pankaj Pant, Vidya Neerkundar. 21-25 [doi]
• Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault TestingHanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich. 26-30 [doi]
• Functionally-Possible Gate-Exhaustive Bridging FaultsIrith Pomeranz. 31-35 [doi]
• Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime StatesAnlin Liu, Tianyao Lu, Yuhao Xi, Yangfan Liu, Peng Liu. 36-40 [doi]
• A Cell-aware Transistor State Stress Model and its Application for Quality MeasurementStephan Eggersglüß, Andreas Glowatz. 41-45 [doi]
• Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnectsZhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 46-50 [doi]
• Handling Die-to-Die I/O Pads for 3DIC Interconnect TestsSandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora. 51-55 [doi]
• Probe Card Ground Noise Canceling CircuitSeongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi, Chanyeol Park, SunYong Park, Woonphil Yang. 56-60 [doi]
• Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCsHiroyuki Iwata, Mahmoud AbdAlwahab, Ron Press, Ohki Sugiura. 61-65 [doi]
• Scalable BIST for Linearity Testing of Sigma-Delta ModulatorsKrishna Pramod Madabhushi, Trevor LaBanz, Sudip Dandnaik, Eslam Hag. 66-70 [doi]
• Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing TechniquesAleksa Deric, Kyle Mitard, Shahin Tajik, Daniel E. Holcomb. 71-75 [doi]
• Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer VariantShu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao. 76-80 [doi]
• Cross-Layer Reliability Evaluation of In-Memory Similarity ComputationAli Nezhadi, Mahta Mayahinia, Mehdi B. Tahoori. 81-85 [doi]
• Design-for-Test for Silicon Photonic CircuitsPratishtha Agnihotri, Priyank Kalla, Steve Blair. 86-90 [doi]
• Defects, Fault Modeling, and Test Development Framework for FeFETsChanghao Wang, Sicong Yuan, Hanzhi Xun, Chaobo Li, Mottaqiallah Taouil, Moritz Fieback, Danyang Chen, Xiuyan Li, Lin Wang, Riccardo Cantoro, Chujun Yin, Said Hamdioui. 91-95 [doi]
• Defect Analysis for FeFETs using a Compact ModelDhruv Thapar, Arjun Chaudhuri, Kai Ni, Krishnendu Chakrabarty. 96-100 [doi]
• Locked-by-Design: Enhancing White-box Logic Obfuscation with Effective Key MutationLeon Li, Alex Orailoglu. 101-105 [doi]
• FAT-RABBIT: Fault-Aware Training towards Robustness AgainstBit-flip Based Attacks in Deep Neural NetworksHossein Pourmehrani, Javad Bahrami, Parsa Nooralinejad, Hamed Pirsiavash, Naghmeh Karimi. 106-110 [doi]
• WM-Graph: Graph-Based Approach for Wafermap AnalyticsMin-Jian Yang, Yueling Jenny Zeng, Li-C. Wang. 111-120 [doi]
• Boost CPU Turbo Yield Utilizing Explainable Artificial IntelligenceC.-W. Lin, P. C. Tsao, Ross Lee, Khim Koh, Y. J. Ting, Jennifer Hsiao, C. T. Lai, T. H. Lee. 121-128 [doi]
• A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test ReductionMehul D. Shroff, Nguyen Nguyen, Kiran Sunny Thota. 129-138 [doi]
• Adaptive Diagnosis Points for 100% Chain Diagnosis CoverageWu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey. 139-148 [doi]
• Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based ChipsYi-Chun Huang, Pei Yun Lin, Jin-Fu Li 0001, Hong-Siang Fu, Yung-Ping Lee. 149-156 [doi]
• Delay Monitoring Under Different PVT Corners for Test and Functional OperationHari Addepalli, Jiezhong Wu, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. 157-166 [doi]
• High-Bandwidth IJTAG over SSNJonathan Gaudet, Jan Burchard, Matthias Kampmann, Jean-François Côté, Tim Callahan, Hung Ho Chai, Ivy Ee Hsia Lim, Lori Schramm, Olga Przybysz, Marta Stepniewska, Sascha Ochsenknecht, Michal Olejarz, Martin Keim. 167-176 [doi]
• *Ashish Reddy Bommana, Farshad Firouzi, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 177-186 [doi]
• qFD: Coherent and Depolarizing Fault Diagnosis for Quantum ProcessorsYen-Wei Li, Cheng-Yun Hsieh, Meng-Chen Wu, James Chien-Mo Li. 187-196 [doi]
• Toward Fault-Tolerant Applications on Reconfigurable Systems-on-ChipCorrado De Sio, Luca Sterpone. 197-206 [doi]
• Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource-constrained IoT Edge DevicesGeancarlo Abich, Ricardo Augusto da Luz Reis, Luciano Ost. 207-216 [doi]
• Electrical Stimulus Based Calibration of MEMS AccelerometerIshaan Bassi, Sule Ozev. 217-225 [doi]
• Generation and Quality Evaluation of Synthetic Process Control Monitoring DataMatthew Nigh, John M. Carulli, Yiorgos Makris. 226-232 [doi]
• Safety-Guided Test Generation for Structural FaultsXuanyi Tan, Dhruv Thapar, Deepesh Sahoo, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Rubin A. Parekhji. 233-242 [doi]
• E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through TelemetryEduardo Ortega, Jonti Talukdar, Woohyun Paik, Fei Su, Rita Chattopadhyay, Krishnendu Chakrabarty. 243-252 [doi]
• Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center ProcessorSuriyaprakash Natarajan, Chaitali S. Oak, Vijay Kakollu, Nipun Chaplot, Soham Roy, Apurva Lonkar, Gerardo J. Perfecto Reyes. 253-260 [doi]
• Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing TestChi Lai, Shi-Yu Huang. 261-269 [doi]
• A Fast and Efficient Graph-Based Methodology for Cell-Aware Model GenerationGianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard 0001, Arnaud Virazel. 270-279 [doi]
• Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologiesJaehoon Lee, HyeonUk Son, Seohyun Kang, Dahyun Kang, Dongkwan Han, Jongsin Yun, Artur Pogiel, Etienne Racine, Krzysztof Jurga, Lori Schramm, Martin Keim. 280-285 [doi]
• Diagnosis of Defects on Global SignalsXinyang Zhao, Baohua Wang, Yin Zhang, Weiming Zhang, Xiaotian Ding, Yu Huang. 286-292 [doi]
• Predictive Testing for Aging in SRAMs and MitigationYunkun Lin, Mingye Li, Sandeep Gupta 0001. 293-302 [doi]
• SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP CounterfeitsGalib Ibne Haidar, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi. 303-312 [doi]
• Test Data Encryption with a New Stream CipherJanusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak. 313-322 [doi]
• Towards Machine-Learning-based Oracle-Guided Analog Circuit DeobfuscationDipali Jain, Guangwei Zhao, Rajesh Datta, Kaveh Shamsi. 323-332 [doi]
• * for Multi-die PackagesSaurabh Upadhyay, Ahmet Tokuz. 333-338 [doi]
• Digital Scan and ATPG for Analog CircuitsStephen Sunter, Krzysztof Jurga. 339-347 [doi]
• Functional State Extraction using Scan DFTIlya Wagner, Pankaj Pant, Arani Sinha. 348-353 [doi]
• MBIST-based MRAM defect screening for safety-critical applicationsSina Bakhtavari Mamaghani, Jongsin Yun, Martin Keim, Mehdi B. Tahoori. 354-363 [doi]
• Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?Sicong Yuan, Hanzhi Xun, Woojin Kim, Siddharth Rao, Erik Jan Marinissen, Sebastien Couet, Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui. 364-373 [doi]
• Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMsHanzhi Xun, Moritz Fieback, Mohammad Amin Yaldagard, Sicong Yuan, Erbing Hua, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui. 374-383 [doi]
• Power-Aware Test Scheduling for Memory BISTAlbert Au, Michal Kçpinski, Makary Orczyk, Artur Pogiel. 384-390 [doi]
• Deterministic In-Fleet Scan Test for a Cloud Computing PlatformDan Trock, Subramanian Mahadevan, Nilanjan Mukherjee 0001, Lee Harrison, Janusz Rajski, Jerzy Tyszer. 391-399 [doi]
• A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHSKunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun. 400-406 [doi]
• LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node UpsetsAlan S.-M. Liu, Lowry P.-T. Wang, Charles H.-P. Wen, Herming Chiueh. 407-416 [doi]
• A graph-based algorithm for NVM address decoders testingPierre Scaramuzza, Thomas Kern, Matteo Coppetta, Alessandro Grossi, Rudolf Ullmann. 417-425 [doi]
• TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional ClusteringSuhasini Komarraju, Mohamed Mejri, Abhijit Chatterjee, Suriyaprakash Natarajan, Prashant Goteti. 426-435 [doi]
• AI-Enabled Board Level Vibration Testing: Unveiling The Physics of DegradationVarun Thukral, Chen He, Rebecca Chen, Letian Zhang, Romuald Roucou, Michiel van Soestbergen, Jeroen J. M. Zaal, Rene Rongen, Willem D. van Driel, G. Q. Zhang. 436-444 [doi]
• Virtual Test Development Using Pre-Silicon Verification EnvironmentE. Aderholz, Q. Atol, B. Baptist, R. Holzner, R. Ignacio, V. Kamanuri, A. Kun, K. Ma, B. Mariacher, O. Pfabigan, A. Przybilla, D. Samardzic, F. Schlagbauer, M. Schleicher, J. P. Valiente, E. Vargas, K. Vinod, O. Zikulnig. 445-450 [doi]
• Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open StandardSandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar. 451-459 [doi]