Table of Contents

• MT-DLA: An Efficient Multi-Task Deep Learning Accelerator DesignMengdi Wang, Bing Li, Ying Wang, Cheng Liu, Xiaohan Ma, Xiandong Zhao, Lei Zhang. 1-8 [doi]
• Bitwise Neural Network Acceleration Using Silicon PhotonicsKyle Shiflett, Avinash Karanth, Ahmed Louri, Razvan C. Bunescu. 9-14 [doi]
• Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix MultiplicationYilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang. 15-20 [doi]
• Tenet: A Neural Network Model Extraction Attack in Multi-core ArchitectureChengsi Gao, Bing Li, Ying Wang, Weiwei Chen, Lei Zhang. 21-26 [doi]
• LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit SynthesisMuhammad Awais 0009, Hassan Ghasemzadeh Mohammadi 0002, Marco Platzner. 27-32 [doi]
• EPEX: Processor Verification by Equivalent Program ExecutionLucas Klemmer, Daniel Große. 33-38 [doi]
• IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement LearningNan Wu, Yuan Xie 0001, Cong Hao. 39-44 [doi]
• SFP: Smart File-Aware Prefetching for Flash based Storage SystemsHan Wang, Longfei Luo, Liang Shi, Changlong Li, Chun Jason Xue, Qingfeng Zhuge, Edwin H.-M. Sha. 45-50 [doi]
• Equivalence Checking for Superconducting RSFQ Logic CircuitsRongliang Fu, Junying Huang, Zhimin Zhang. 51-56 [doi]
• CAMeleon: Reconfigurable B(T)CAM in Computational RAMZamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jian-Ping Wang, Ulya R. Karpuzcu. 57-63 [doi]
• A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural NetworksZijing Niu, Honglan Jiang, Mohammad Saeed Ansari, Bruce F. Cockburn, Leibo Liu, Jie Han 0001. 65-70 [doi]
• O(1) with RRAM-based In-Memory AcceleratorTao Song, Xiaoming Chen 0003, Yinhe Han. 71-76 [doi]
• On the Vulnerability of Hardware Masking in Practical ImplementationsSatwik Patnaik. 77-82 [doi]
• The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORingYongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui. 83-88 [doi]
• APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural NetworkPranesh Santikellur, Rijoy Mukherjee, Rajat Subhra Chakraborty. 89-94 [doi]
• Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons LearnedAhmad-Reza Sadeghi, Jeyavijayan Rajendran, Rahul Kande. 95-100 [doi]
• Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMsBobby Bose, Ishan G. Thakkar. 101-107 [doi]
• Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic MapsPartha Sarathi Paul 0002, Maisha Sadia, Md Razuan Hossain, Barry J. Muldrey, Md Sakib Hasan. 109-114 [doi]
• CNN-DMA: A Predictable and Scalable Direct Memory Access Engine for Convolutional Neural Network with Sliding-window FilteringZheng Wang, Zhuo Wang, Jian Liao, Chao Chen 0022, Yongkui Yang, Bo Dong, Weiguang Chen, Wenxuan Chen, Ming Lei, Weiyu Guo, Rui Chen, Yi Peng, Zhibin Yu. 115-121 [doi]
• Improving Lifetime of Non-Volatile Memory Caches by Logical PartitioningS. Sivakumar, T. M. Abdul Khader, John Jose. 123-128 [doi]
• Relaxed Placement: Minimizing Shift Operations for Racetrack Memory in Hybrid SPMRui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Liang Shi, Shouzhen Gu, Yan Hou. 129-134 [doi]
• Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-DesignM. D. Arafat Kabir, Dusan Petranovic, Yarui Peng. 135-140 [doi]
• Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up TableWei Zhang, Yongxiao Zhou, Tsung-Yi Ho, Hailong Yao. 141-146 [doi]
• A Composable Glitch-Aware Delay ModelJürgen Maier 0002, Daniel Öhlinger, Ulrich Schmid 0001, Matthias Függer, Thomas Nowak. 147-154 [doi]
• Evolving Trust for High Consequence MicroelectronicsVivian Guzman Kammler. 155 [doi]
• 3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency AccelerationYao Chen, Cole Hawkins, Kaiqi Zhang, Zheng Zhang 0005, Cong Hao. 157-162 [doi]
• Accommodating Transformer onto FPGA: Coupling the Balanced Model Compression and FPGA-Implementation OptimizationPanjie Qi, Yuhong Song, Hongwu Peng, Shaoyi Huang, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 163-168 [doi]
• HMC-TRAN: A Tensor-core Inspired Hierarchical Model Compression for Transformer-based DNNs on GPUShaoyi Huang, Shiyang Chen, Hongwu Peng, Daniel Manu, Zhenglun Kong, Geng Yuan, Lei Yang, Shusen Wang, Hang Liu 0001, Caiwen Ding. 169-174 [doi]
• Co-Exploration of Graph Neural Network and Network-on-Chip Design Using AutoMLDaniel Manu, Shaoyi Huang, Caiwen Ding, Lei Yang. 175-180 [doi]
• A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR DropSayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj, Ioannis Savidis, Houman Homayoun, Avesta Sasan. 181-187 [doi]
• On the Adversarial Robustness of Quantized Neural NetworksMicah Gorsline, James Smith, Cory E. Merkel. 189-194 [doi]
• Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band FilteringNeha Nagarkar, Khaled N. Khasawneh, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao. 195-200 [doi]
• Adversarial Attack Mitigation Approaches Using RRAM-Neuromorphic ArchitecturesSiddharth Barve, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao, Rashmi Jha. 201-206 [doi]
• The Curious Case of Trusted IC Provisioning in Untrusted Testing FacilitiesSandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia. 207-212 [doi]
• SAT-attack Resilience Measure for Access Restricted CircuitsSaran Phatharodom, Avesta Sasan, Ioannis Savidis. 213-220 [doi]
• RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted CircuitsShervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan. 221-228 [doi]
• Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware SecurityAbubakr Abdulgadir, Sammy Lin, Farnoud Farahmand, Jens-Peter Kaps, Kris Gaj. 229-234 [doi]
• RECOIN: A Low-Power Processing-in-ReRAM Architecture for Deformable ConvolutionCheng Chu, Fan Chen, Dawen Xu 0002, Ying Wang 0001. 235-240 [doi]
• Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning ProcessorsBo Jiao, Haozhe Zhu, Jinshan Zhang 0006, Shunli Wang, Xiaoyang Kang, Lihua Zhang, Mingyu Wang, Chixiao Chen. 241-246 [doi]
• DeepDive: An Integrative Algorithm/Architecture Co-Design for Deep Separable Convolutional Neural NetworksMohammadreza Baharani, Ushma Sunil, Kaustubh Manohar, Steven Furgurson, Hamed Tabkhi. 247-252 [doi]
• IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted AccelerationFangxin Liu, Wenbo Zhao, Zongwu Wang, Tao Yang, Li Jiang. 253-258 [doi]
• qMC: A Formal Model Checking Verification Framework For Superconducting LogicMustafa Munir, Aswin Gopikanna, Arash Fayyazi, Massoud Pedram, Shahin Nazarian. 259-264 [doi]
• Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative StudyShaahin Angizi, Arman Roohi, MohammadReza Taheri, Deliang Fan. 265-270 [doi]
• A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical SignalsMingdai Yang, Mohammad Reza Jokar, Junyi Qiu, Qiuwen Lou, Yuming Liu, Aditi Udupa, Frederic T. Chong, John M. Dallesasse, Milton Feng, Lynford L. Goddard, X. Sharon Hu, Yanjing Li. 271-276 [doi]
• MEDASec: Logic Encryption Scheme for Micro-electrode-dot-array Biochips IP ProtectionChen Dong, Lingqing Liu, Ximeng Liu, Huangda Liu, Sihuang Lian, null null. 277-282 [doi]
• Domain Isolation in FPGA-Accelerated Cloud and Data Center ApplicationsJoel Mandebi Mbongue, Sujan Kumar Saha, Christophe Bobda. 283-288 [doi]
• Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCsHui Chen, Zihao Zhang, Peng Chen, Shien Zhu, Weichen Liu. 289-294 [doi]
• Predictive Warp Scheduling for Efficient Execution in GPGPUAbhinish Anand, Winnie Thomas, Suryakant Toraskar, Virendra Singh. 295-300 [doi]
• A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation EnvironmentsAibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. 301-306 [doi]
• Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable CircuitsNeha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard 0001. 307-312 [doi]
• Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight MappingYu Ma, Linfeng Zheng, Pingqiang Zhou. 313-318 [doi]
• An Air Force Perspective on the Application of Machine Learning for Microelectronics Design and SecurityPompei Len Orlando. 319 [doi]
• Minimally Invasive HW/SW Co-debug Live Visualization on Architecture LevelPascal Pieper, Ralf Wimmer 0001, Gerhard Angst, Rolf Drechsler. 321-326 [doi]
• PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC AnalysisZhou Jin, Tian Feng, Yiru Duan, Xiao Wu, Minghou Cheng, Zhenya Zhou, Weifeng Liu. 327-332 [doi]
• ALPINE: An Agile Processing-in-Memory Macro Compilation FrameworkJinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu, Lihua Zhang, Chixiao Chen. 333-338 [doi]
• MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded SystemsSiva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar 0001. 339-346 [doi]
• Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM SupportChen Nie, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, Zhezhi He. 347-352 [doi]
• Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech ProcessingShiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang, C.-J. Richard Shi. 353-358 [doi]
• Unlocking Approximations through Selective Source Code TransformationsPrattay Chowdhury, Benjamin Carrión Schäfer. 359-364 [doi]
• Machine Learning Based Acceleration Method for Ordered Escape RoutingZhiyang Chen, Weiqing Ji, Yihao Peng, Datao Chen, Mingyu Liu, Hailong Yao. 365-370 [doi]
• Novel Approximate Multiplier Designs for Edge Detection ApplicationYashaswi Mannepalli, Viraj Bharadwaj Korede, Madhav Rao. 371-377 [doi]
• Accelerating AI Applications using Analog In-Memory Computing: Challenges and OpportunitiesShravya Channamadhavuni, Sven Thijssen, Sumit Kumar Jha 0001, Rickard Ewetz. 379-384 [doi]
• A Comprehensive Analysis of Low-Impact Computations in Deep Learning WorkloadsHengyi Li, Zhichen Wang, Xuebin Yue, Wenwen Wang, Hiroyuki Tomiyama, Lin Meng. 385-390 [doi]
• An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance DatasetMingshuo Liu, Kevin Han, Shiyi Luo, Mingze Pan, Mousam Hossain, Bo Yuan 0001, Ronald F. DeMara, Yu Bai 0004. 391-396 [doi]
• Real-Time and Robust Hyperdimensional ClassificationAlejandro Hernández-Cano, Cheng Zhuo, Xunzhao Yin, Mohsen Imani. 397-402 [doi]
• IVcache: Defending Cache Side Channel Attacks via Invisible AccessesYanan Guo, Andrew Zigerelli, Youtao Zhang, Jun Yang 0002. 403-408 [doi]
• Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-VGeraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib. 409-414 [doi]
• Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic LockingZhiming Zhang, Ivan Miketic, Emre Salman, Qiaoyan Yu. 415-420 [doi]
• Tuning Memory Fault Tolerance on the EdgeAlex K. Jones, Stephen Longofono, Sébastien Ollivier, Donald Kline Jr., Jiangwei Zhang, Rami G. Melhem. 421-424 [doi]
• Socially-Distant Hands-On Labs for a Real-time Digital Signal Processing CoursePatrick Schaumont. 425-430 [doi]
• ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA BoardZhixiong Di, Yongming Tang, Jiahua Lu, Zhaoyang Lv. 431-436 [doi]
• Experiences with Remote Teaching an Embedded Systems CourseJohn A. Nestor. 437-442 [doi]
• Provably Accurate Memory Fault Detection Method for Deep Neural NetworksOmid Aramoon, Gang Qu. 443-448 [doi]
• Unpaired Image-to-Image Translation Network for Semantic-based Face Adversarial Examples GenerationJiliang Zhang 0002, Junjie Hou. 449-454 [doi]
• DNN Intellectual Property Protection: Taxonomy, Attacks and Evaluations (Invited Paper)Mingfu Xue, Jian Wang 0038, Weiqiang Liu. 455-460 [doi]
• Security Enhancements for Approximate Machine LearningHe Li, Yaru Pang, Jiliang Zhang 0002. 461-466 [doi]
• Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offsShamiul Alam, Nazmul Amin, Sumeet Kumar Gupta, Ahmedullah Aziz. 467-472 [doi]
• Overview of Ferroelectric Memory Devices and Reliability Aware Design OptimizationShan Deng, Zijian Zhao, Santosh Kurinec, Kai Ni 0006, Yi Xiao, Tongguang Yu, Vijaykrishnan Narayanan. 473-478 [doi]
• Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching ApplicationsNuo Xiu, Yiming Chen, Guodong Yin, Xiaoyang Ma, Huazhong Yang, Sumitha George, Xueqing Li. 479-484 [doi]
• Ferroelectric-based Accelerators for Computationally Hard ProblemsMohammad Khairul Bashar, Jaykumar Vaidya, R. S. Surya Kanthi, Chonghan Lee, Feng Shi, Vijaykrishnan Narayanan, Nikhil Shukla. 485-489 [doi]