Abstract is missing.
- Analysis of Single Event Upsets Based on Digital Cameras with Very Small PixelsGlenn H. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Israel Koren, Zahava Koren. 1-6 [doi]
- Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test SetIrith Pomeranz. 1-6 [doi]
- A Method to Model Statistical Path Delays for Accurate Defect CoveragePavan Kumar Javvaji, Spyros Tragoudas. 1-6 [doi]
- Fast Dynamic Device Authentication Based on Lorenz Chaotic SystemsLake Bu, Hai Cheng, Michel A. Kinsy. 1-6 [doi]
- Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic CircuitsSemiu A. Olowogemo, William H. Robinson, Daniel B. Limbrick. 1-6 [doi]
- A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-ChipAlexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Raoul Velazco. 1-6 [doi]
- Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-ElementYuta Yamamoto, Kazuteru Namba. 1-6 [doi]
- Evaluating the Resilience of Parallel ApplicationsMark Wilkening, Fritz Previlon, David R. Kaeli, Sudhanva Gurumurthi, Steven Raasch, Vilas Sridharan. 1-6 [doi]
- Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting TestsNaixing Wang, Irith Pomeranz, Brady Benware, M. EnamulAmyeen, Srikanth Venkataraman. 1-6 [doi]
- FPGA SEE Test with Ultra-High Energy Heavy IonsGianluca Furano, Antonis Tavoularis, Lucana Santos, Veronique Ferlet-Cavrois, Cesar Boatella, Ruben Garcia Alia, Pablo Fernandez Martinez, Maria Kastriotou, Vanessa Wyrwoll, Salvatore Danzeca, Maris Tali, Dejan Gacnik, Iztok Kramberger, Lars Juul, Konstantinos Maragos, George Lentaris. 1-4 [doi]
- Threshold Voltage Extraction Using Static NBTI AgingPuneet Ramesh Savanur, Spyros Tragoudas. 1-6 [doi]
- Investigation of Mean-Error Metrics for Testing Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. 1-6 [doi]
- A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS TechnologyGeorgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor E. Evmorfopoulos, George Dimitriou, Georgios I. Stamoulis. 1-6 [doi]
- MATS**: An On-Line Testing Approach for Reconfigurable Embedded MemoriesLudovica Bozzoli, Luca Sterpone. 1-6 [doi]
- Performance-Based and Aging-Aware Resource Allocation for Concurrent GPU ApplicationsZois-Gerasimos Tasoulas, Ryan Guss, Iraklis Anagnostopoulos. 1-6 [doi]
- Physics-Informed Machine Learning for DRAM Error ModelingElisabeth Baseman, Nathan DeBardeleben, Sean Blanchard, Juston Moore, Olena Tkachenko, Kurt B. Ferreira, Taniya Siddiqua, Vilas Sridharan. 1-6 [doi]
- Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi DecodersZhen Gao, Lina Yan, Jinhua Zhu, Ruishi Han, Pedro Reviriego. 1-6 [doi]
- Multiple Fault Detection in Nano Programmable Logic ArraysPilin Junsangsri, Fabrizio Lombardi. 1-6 [doi]
- State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial ReconfigurationMarkus Schutz, Andreas Steininger, Florian Huemer, Jakob Lechner. 1-6 [doi]
- 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access ControlVishal Gupta, Saurabh Khandelwal, Jimson Mathew, Marco Ottavi. 1-6 [doi]
- Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep ProcessorsA. Floridia, E. Sanchez. 1-6 [doi]
- Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMsAbhishek Das, Nur A. Touba. 1-6 [doi]
- Complementary Resistive Switch SensingDanilo Pellegrini, Marco Ottavi, Eugenio Martinelli, Corrado Di Natale. 1-5 [doi]