Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits

Semiu A. Olowogemo, William H. Robinson, Daniel B. Limbrick. Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018. pages 1-6, IEEE Computer Society, 2018. [doi]

Abstract

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