Yuta Yamamoto, Kazuteru Namba. Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018. pages 1-6, IEEE Computer Society, 2018. [doi]
Abstract is missing.