Yuta Yamamoto, Kazuteru Namba. Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018. pages 1-6, IEEE Computer Society, 2018. [doi]
@inproceedings{YamamotoN18-1,
title = {Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element},
author = {Yuta Yamamoto and Kazuteru Namba},
year = {2018},
doi = {10.1109/DFT.2018.8602841},
url = {https://doi.org/10.1109/DFT.2018.8602841},
researchr = {https://researchr.org/publication/YamamotoN18-1},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018},
publisher = {IEEE Computer Society},
isbn = {978-1-5386-8398-9},
}