Table of Contents

• Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside TestsIrith Pomeranz. 1-4 [doi]
• Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact ModelsDan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux. 1-6 [doi]
• On the testing of special memories in GPGPUsJosie E. Rodriguez Condia, Matteo Sonza Reorda. 1-6 [doi]
• Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAsCristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele. 1-6 [doi]
• Muon-Ra: Quantum random number generation from cosmic raysHomer Gamil, Pranav Mehta, Eduardo Chielle, Adriano Di Giovanni, Mohammed Nabeel, Francesco Arneodo, Michail Maniatakos. 1-6 [doi]
• Soft Error Tolerance of Power-Supply-Noise Hardened LatchesYukiya Miura, Yuya Kinoshita. 1-6 [doi]
• A Low Capture Power Oriented X-Identification-Filling Co-Optimization MethodToshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai. 1-4 [doi]
• Temporary Laser Fault Injection into Flash Memory: Calibration, Enhanced Attacks, and CountermeasuresKathrin Garb, Johannes Obermaier. 1-7 [doi]
• Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault AnalysisAna Lasheras, Ramon Canal, Eva Rodríguez, Luca Cassano. 1-6 [doi]
• Defect Characterization of Spintronic-based Neuromorphic CircuitsChristopher Münch, Mehdi B. Tahoori. 1-4 [doi]
• Impact of Aging on Soft Error Susceptibility in CMOS CircuitsAmbika Prasad Shah, Patrick Girard 0001. 1-4 [doi]
• Machine Learning Clustering Techniques for Selective Mitigation of Critical Design FeaturesThomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone. 1-7 [doi]
• A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace ApplicationsPablo Ilha Vaz, Patrick Girard 0001, Arnaud Virazel, Hassen Aziza. 1-6 [doi]
• A Test Sensitization State Compaction Method on Controller AugmentationYuki Ikegaya, Toshinori Hosokawa, Yuta Ishiyama, Hiroshi Yamazaki. 1-6 [doi]
• Dependable Deep Learning: Towards Cost-Efficient Resilience of Deep Neural Network Accelerators against Soft Errors and Permanent FaultsMuhammad Abdullah Hanif, Muhammad Shafique 0001. 1-4 [doi]
• High-level Modeling of Manufacturing Faults in Deep Neural Network AcceleratorsShamik Kundu, Ahmet Soyyigit, Khaza Anuarul Hoque, Kanad Basu. 1-4 [doi]
• Spiking Neuron Hardware-Level Fault ModelingSarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos. 1-4 [doi]
• Encoded Check Driven Concurrent Error Detection in Particle Filters for Nonlinear State EstimationChandramouli N. Amarnath, Md Imran Momtaz, Abhijit Chatterjee. 1-6 [doi]
• A Framework and Protocol for Dynamic Management of Fault Tolerant Systems in Harsh EnvironmentsEduardo Weber Wächter, Server Kasap, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier. 1-6 [doi]
• In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-FlopsSarah Azimi, Corrado De Sio, Luca Sterpone. 1-6 [doi]
• Explainability and Dependability Analysis of Learning Automata based AI HardwareRishad A. Shafik, Adrian Wheeldon, Alex Yakovlev. 1-4 [doi]
• Representing Gate-Level SET Faults by Multiple SEU Faults at RTLAhmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001. 1-6 [doi]
• Fast BCH 1-Bit Error Correction Combined with Fast Multi-Bit Error DetectionChristian Schulz-Hanke. 1-5 [doi]
• Life-Time Prognostics of Dependable VLSI-SoCs using Machine-learningLeila Bagheriye, Ghazanfar Ali, Hans G. Kerkhoff. 1-4 [doi]
• SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware FeaturesHan Wang, Hossein Sayadi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun. 1-6 [doi]
• On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life TestYousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura. 1-6 [doi]
• Leveraging CMOS Aging for Efficient Microelectronics DesignAntonio Leonel Hernández Martínez, S. Saqib Khursheed, Daniele Rossi 0001. 1-4 [doi]
• A Secure Scan Controller for Protecting Logic LockingQuang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. 1-6 [doi]
• Leveraging reuse and endurance by efficient mapping and placement for NVM-based FPGAsJoão Paulo Cardoso de Lima, Rafael Fão de Moura, Luigi Carro. 1-6 [doi]
• Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded ApplicationZahra Kazemi, Mahdi Fazeli, David Hély, Vincent Beroulle. 1-6 [doi]
• Yield Estimation of a Memristive Sensor ArrayVishal Gupta, Saurabh Khandelwal, Giulio Panunzi, Eugenio Martinelli, Said Hamdioui, Abusaleh M. Jabir, Marco Ottavi. 1-2 [doi]
• Reduced-Precision DWC for Mixed-Precision GPUsFernando Fernandes dos Santos, Marcelo Brandalero, Pedro Martins Basso, Michael Hübner, Luigi Carro, Paolo Rech. 1-6 [doi]
• Broadside ATPG for Low Power Trojans Detection using Built-in Current SensorsBasim Shanyour, Spyros Tragoudas. 1-3 [doi]
• Industrial Practices in Low-Power Robust DesignC. P. Ravikumar. 1-4 [doi]
• PISA: Power-robust Multiprocessor Design for Space ApplicationsAleksandar Simevski, Oliver Schrape, Carlos Benito, Milos Krstic, Marko S. Andjelkovic. 1-6 [doi]
• A self-scrubbing scheme for embedded systems in radiation environmentsYufan Lu, Xiaojun Zhai, Sangeet Saha, Shoaib Ehsan, Klaus D. McDonald-Maier. 1-4 [doi]
• A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 SystemMichele Portolan, R. S. Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, K. S. Kannan, M. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, S. Mir. 1-4 [doi]
• Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICsFlorence Azaïs, S. Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard 0001, Vincent Kerzèrho, L. Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssadel, Arnaud Virazel. 1-4 [doi]
• An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power BehaviorsKazunari Takasaki, Kento Hasegawa, Ryoichi Kida, Nozomu Togawa. 1-4 [doi]
• Single Phase Clock Based Radiation Tolerant D Flip-flop CircuitA. Jain, Andrea Veggetti, Dennis Crippa, A. Benfante, Simone Gerardin, Marta Bagatin. 1-6 [doi]
• Automatic Fault Simulators for Diagnosis of Analog SystemsTommaso Melis, Emmanuel Simeu, Etienne Auvray. 1-6 [doi]
• An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAMPanagiota Papavramidou, Michael Nicolaidis, Patrick Girard 0001. 1-6 [doi]
• Reduced Fault Coverage as a Target for Design Scaffolding SecurityIrith Pomeranz, Sandip Kundu. 1-6 [doi]
• Error Resilient Machine Learning for Safety-Critical Systems: Position PaperKarthik Pattabiraman, Guanpeng Li, Zitao Chen. 1-4 [doi]
• Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning MethodsTatsuki Kurihara, Kento Hasegawa, Nozomu Togawa. 1-4 [doi]