Table of Contents

• NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed LinksMahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey. 1-7 [doi]
• Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML SystemsShail Dave, Alberto Marchisio, Muhammad Abdullah Hanif, Amira Guesmi, Aviral Shrivastava, Ihsen Alouani, Muhammad Shafique 0001. 1-14 [doi]
• Innovative Practices Track: Test of 3D ICs & ChipletsSandeep Kumar Goel, Sandeep Pendharkar, Chunsheng Liu. 1 [doi]
• Fast Test Generation for Structurally Similar CircuitsJerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. 1-7 [doi]
• A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault DetectionMarcel Merten, Sebastian Huhn 0001, Rolf Drechsler. 1-7 [doi]
• Special Session: A Call to Standardize Chip-let Interconnect TestingSreejit Chakravarty. 1-3 [doi]
• Special Session: Closed Chassis Platform Debug of Compute Systems using the Functional Ubiquitous USB Type-C ReceptacleSankaran M. Menon, Rolf Kühnis. 1-4 [doi]
• Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel ConfigurationsShi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang 0014, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy. 1-7 [doi]
• Innovative Practices Track: Novel Methods for Validation and TestNitin Chaudhary. 1 [doi]
• Innovation Practices Track: Security in Test and Test for SecurityGang Qu 0001, Benjamin Tan 0001, Kuheli Pratihar, Debdeep Mukhopadhyay, Ramesh Karri. 1 [doi]
• MBIST-based Trim-Search Test Time Reduction for STT-MRAMChristopher Münch, Jongsin Yun, Martin Keim, Mehdi B. Tahoori. 1-7 [doi]
• Special Session: A Testability Practitioner's Guide to ChipletsAbram Detofsky. 1-2 [doi]
• Innovative Practices Track: High Speed Test FabricBala Tarun Nelapatla, Rahul Singhal, Michael Daub, Zoran Stanojevics. 1 [doi]
• Special Session: On the Reliability of Conventional and Quantum Neural Network HardwareMehdi Sadi, Yi He, Yanjing Li, Mahabubul Alam, Satwik Kundu, Swaroop Ghosh, Javad Bahrami, Naghmeh Karimi. 1-12 [doi]
• Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICsAntonios Pavlidis, Eric Faehn, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos. 1-8 [doi]
• Innovative Practices Track: Innovative Analog Circuit Testing TechnologiesChris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi 0001, Keno Sato, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa. 1 [doi]
• Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI SystemsRubin A. Parekhji. 1 [doi]
• FIFO Topology Aware Stalling for Accelerating Coverage Convergence of Stalling RegressionsDebarshi Chatterjee, Parth Lathigara, Siddhanth Dhodhi, Chad Parsons. 1-7 [doi]
• Performance Degradation Monitoring for Analog Circuits Using Lightweight Built-in ComponentsBora Bilgic, Sule Ozev. 1-7 [doi]
• Innovative Practices Track: Next Generation Test StandardsArani Sinha. 1 [doi]
• Innovation Practices Track: Silicon Telemetry for DependabilityFei Su, Stephen Crosher, Andrea Matteucci, Yuwen Zou. 1 [doi]
• Exploring Model-based Failure Prediction of Passive Bio-electro-mechanical ImplantsDaniel W. Gulick, Yuna Jung, Seunghyun Lee, Sule Ozev, Jennifer Blain Christen. 1-7 [doi]
• Semi-Supervised Root-Cause Analysis with Co-Training for Integrated SystemsRenjian Pan, Xin Li 0001, Krishnendu Chakrabarty. 1-7 [doi]
• Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/OAmit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal. 1-7 [doi]
• Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic CircuitsZiqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal. 1-7 [doi]
• Special Session: Calibrating mismatch in an ISFET with a Floating-GateSahil Shah, Jennifer Blain Christen. 1-4 [doi]
• Special Session: Testing and Characterization for Large-Scale Programmable Analog SystemsJennifer Hasler. 1-5 [doi]
• Special Session: Fault Criticality Assessment in AI AcceleratorsArjun Chaudhuri, Jonti Talukdar, Krishnendu Chakrabarty. 1-4 [doi]
• Voltage Tuning for Reliable Computation in Emerging Resistive MemoriesMahta Mayahinia, Atousa Jafari, Mehdi B. Tahoori. 1-7 [doi]
• Fault-tolerant Neuromorphic Computing with Functional ATPG for Post-manufacturing Re-calibrationSoyed Tuhin Ahmed, Mehdi B. Tahoori. 1-7 [doi]
• Special Session: STT-MRAMs: Technology, Design and TestAnteneh Gebregiorgis, Lizhou Wu, Christopher Münch, Siddharth Rao, Mehdi B. Tahoori, Said Hamdioui. 1-10 [doi]
• Fast RF Mismatch Calibration Using Built-in DetectorsMuslum Emir Avci, Sule Ozev, Y. B. Chethan Kumar. 1-7 [doi]
• Machine Learning-Based Overkill Reduction through Inter-Test CorrelationDeepika Neethirajan, V. A. Niranjan, Richard Willis, Amit Nahar, D. Webster, Yiorgos Makris. 1-7 [doi]
• On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas Satheesh, Kuo-Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz. 1-6 [doi]
• All Digital Low-Overhead SAR ADC Built-In Self-Test for Fault Detection and DiagnosisMona Ganji, Marampally Saikiran, Degang Chen. 1-7 [doi]
• A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace ApplicationsAibin Yan, Kuikui Qian, Jie Cui 0004, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001. 1-6 [doi]
• Memristor-Specific Failures: New Verification Methods and Emerging Test ProblemsBaishakhi Rani Biswas, Sandeep Gupta. 1-7 [doi]
• Special Session: Test Impact of Multi-Die PackagesVineet Pancholi. 1-2 [doi]
• FSMx: Finite State Machine Extraction from Flattened Netlist With Application to SecurityRasheed Kibria, Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor. 1-7 [doi]
• Rule Generation for Classifying SLT Failed PartsHo-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao. 1-7 [doi]
• Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC SafetyMinqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee. 1 [doi]
• Special Session: Effective In-field Testing of Deep Neural Network Hardware AcceleratorsShamik Kundu, Suvadeep Banerjee, Arnab Raha, Kanad Basu. 1-4 [doi]
• The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite TestingPraise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi 0001, Degang Chen. 1-7 [doi]
• Exploiting post-silicon debug hardware to improve the fault coverage of Software Test LibrariesRiccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda. 1-7 [doi]
• Special Session: Fault-Tolerant Deep Learning: A Hierarchical PerspectiveCheng Liu 0008, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li. 1-12 [doi]
• Innovative Practices Track: Silent Data ErrorsArani Sinha. 1 [doi]
• Methods for testing path delay and static faults in RSFQ circuitsMingye Li, Fangzhou Wang, Sandeep K. Gupta. 1-7 [doi]
• A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level LanguagesJuan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 1-7 [doi]