Table of Contents

• Optimization Space Exploration of Hardware Design for CRYSTALS-KYBERYixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li 0001, Huawei Li. 1-6 [doi]
• Overview of On-Chip Performance Monitors for Clock SignalsShi-Yu Huang. 1-4 [doi]
• On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital SensorMasayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara. 1-6 [doi]
• A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applicationsArbab Alamgir, Abu Khari bin A'Ain, Norlina Paraman, Usman Ullah Sheikh, Ian Andrew Grout. 1-5 [doi]
• ∗Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty. 1-6 [doi]
• Fault and Soft Error Tolerant Delay-Locked LoopJun-Yu Yang, Shi-Yu Huang. 1-6 [doi]
• Pre-silicon Noise to Timing Test MethodologyFern Nee Tan, Jia Yun Chuah. 1-2 [doi]
• Validating GCSE in the scheduling of high-level synthesisJian Hu, Yongyang Hu, Long Yu, Haitao Yang, Yun Kang, Jie Cheng. 1-6 [doi]
• Survey: Hardware Trojan Detection for NetlistYipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang 0002, Xiaowei Li 0001, Huawei Li, Yu Hu 0001. 1-6 [doi]
• Accurate Testing of Precision Voltage Reference by DC-AC ConversionKeno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001. 1-2 [doi]
• A Method to Detect Open Defects in Wire Segments of On-Chip Power GridsKoutaro Hachiya. 1-6 [doi]
• *Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty. 1-6 [doi]
• LUT-based Circuit Approximation with Targeted Error GuaranteesVinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh. 1-6 [doi]
• An effective technique preventing differential cryptanalysis attackMing Wang, Jian Xiao, Zhikuang Cai. 1-6 [doi]
• SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing MechanismGary K.-C. Huang, Dave Y.-W. Lin, John Z.-L. Tang, Charles H.-P. Wen. 1-6 [doi]
• BTI Aging Monitoring based on SRAM Start-up BehaviorShengyu Duan, Peng Wang, Gaole Sai. 1-6 [doi]
• Artificial Neuron Hardware IP VerificationTeo Sje Yin, Soon Ee Ong. 1-2 [doi]
• LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance ImprovementMichihiro Shintani, Tomoki Mino, Michiko Inoue. 1-6 [doi]
• Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog TestingZolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka. 1-6 [doi]
• Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational AmplifiersGaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, Kazumi Hatayama, Haruo Kobayashi 0001. 1-6 [doi]
• An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image SensorFukashi Morishita, Masanori Otsuka, Wataru Saito. 1-6 [doi]
• Systematic Hold-time Fault Diagnosis and Failure Debug in Production ChipsChih-Yan Liu, Mu-Ting Wu, James C.-M. Li, Gaurav Bhargava, Chris Nigh. 1-7 [doi]
• EMI characterization for power conversion circuit with SiC power devicesTakaaki Ibuchi, Tsuyoshi Funaki. 1-6 [doi]
• Exploring the Mysteries of System-Level TestIlia Polian, Jens Anders, Steffen Becker 0001, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer 0002, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner 0001. 1-6 [doi]
• Testing of Configurable 8T SRAMs for In-Memory ComputingJin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun. 1-5 [doi]
• On-chip EOL Prognostics Using Data-Fusion of Embedded Instruments for Dependable MP-SoCsGhazanfar Ali, Leila Bagheriye, Hans A. R. Manhaeve, Hans G. Kerkhoff. 1-6 [doi]
• A Unified Formal Model for Proving Security and Reliability PropertiesWei Hu 0008, Lingjuan Wu, Yu Tai, Jing Tan, Jiliang Zhang 0002. 1-6 [doi]
• *Arjun Chaudhuri, Chunsheng Liu, Xiaoxin Fan, Krishnendu Chakrabarty. 1-6 [doi]
• An ISA-level Accurate Fault Simulator for System-level Fault AnalysisJiang-Tang Xiao, Ting-Shuo Hsu, Christian M. Fuchs, Yu-Teng Chang, Jing-Jia Liou, Harry H. Chen. 1-6 [doi]
• Potentiality of Data Fusion in Analog Circuit Fault DiagnosisManas Kumar Parai, Kasturi Ghosh, Hafizur Rahaman 0001. 1-6 [doi]
• A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node UpsetsAibin Yan, Yan Chen, Jun Zhou 0016, Jie Cui 0004, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. 1-5 [doi]
• Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching OperationAoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato. 1-6 [doi]
• HRAE: Hardware-assisted Randomization against Adversarial Example AttacksJiliang Zhang 0002, Shuang Peng 0010, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang. 1-6 [doi]
• Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETsYohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato. 1-6 [doi]
• Scan Chain Diagnosis-Driven Test Response CompactorJakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban. 1-6 [doi]
• Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond TestingTanusree Kaibartta, G. P. Biswas, Debesh K. Das. 1-6 [doi]
• Unexpected Error Explosion in NAND Flash Memory: Observations and Prediction SchemeYuQian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu. 1-6 [doi]
• CPU Utilization Micro-Benchmarking for RealTime Workload ModelingChee Hoo Kok, Soon Ee Ong. 1-2 [doi]
• A Testability Enhancement Method for the Memristor Ratioed Logic CircuitsLi Qu, Xiaole Cui, Xiaoxin Cui. 1-6 [doi]
• Analysis and Design of Multi-Tone Signal Generation Algorithms for Reducing Crest FactorYukiko Shibasaki, Koji Asami, Riho Aoki, Akemi Hatta, Anna Kuwana, Haruo Kobayashi 0001. 1-6 [doi]