Table of Contents

• Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk PredictionKatayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi. 1-6 [doi]
• Automating Greybox System-Level Test GenerationDenis Schwachhofer, Maik Betka, Steffen Becker 0001, Stefan Wagner 0001, Matthias Sauer 0002, Ilia Polian. 1-4 [doi]
• Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMPJiaoyan Yao, Ying Zhang, Yifeng Hua, Yuanxiang Li, Jizhong Yang, Xin Chen. 1-4 [doi]
• Automating the Generation of Functional Stress Inducing Stimuli for Burn-In TestingNikolaos Ioannis Deligiannis, Tobias Faller, Chenghan Zhou, Riccardo Cantoro, Bernd Becker 0001, Matteo Sonza Reorda. 1-5 [doi]
• Online Performance Monitoring of Neuromorphic Computing SystemsAbhishek Kumar Mishra, Anup Das 0001, Nagarajan Kandasamy. 1-4 [doi]
• Synthesis of IJTAG Networks for Multi-Power Domain Systems on ChipsPayam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn 0001, Rolf Drechsler. 1-6 [doi]
• Dependability of Future Edge-AI Processors: Pandora's BoxManil Dev Gomony, Anteneh Gebregiorgis, Moritz Fieback, Marc Geilen, Sander Stuijk, Jan Richter-Brockmann, Rajendra Bishnoi, Sven Argo, Lara Arche Andradas, Tim Güneysu, Mottaqiallah Taouil, Henk Corporaal, Said Hamdioui. 1-6 [doi]
• Online Fault-Tolerance for Memristive Neuromorphic Fabric Based on Local ApproximationSoyed Tuhin Ahmed, Roman Rakhmatullin, Mehdi B. Tahoori. 1-4 [doi]
• Mismatch Measurement for MIMO mm-Wave Radars via Simple Power MonitorsFerhat Can Ataman, Mohammed Aladsani, Georgios C. Trichopoulos, Y. B. Chethan Kumar, Sule Ozev. 1-6 [doi]
• Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMsHanzhi Xun, Moritz Fieback, Sicong Yuan, Ziwei Zhang, Mottaqiallah Taouil, Said Hamdioui. 1-6 [doi]
• On-Line Testing of Neuromorphic HardwareTheofilos Spyrou, Haralampos-G. Stratigopoulos. 1-6 [doi]
• DEV-PIM: Dynamic Execution Validation with Processing-in-MemoryAlperen Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik, Sakir Sezer, Marco Ottavi, Oguz Ergin. 1-6 [doi]
• Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit ApplicationsFrancesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen. 1-6 [doi]
• harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNsMarcello Traiola, Angeliki Kritikakou, Olivier Sentieys. 1-6 [doi]
• Evaluating the Prevalence of SFUs in the Reliability of GPUsJosie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda. 1-6 [doi]
• Approximate Communication: Balancing Performance, Power, Reliability, and SafetyAbdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand. 1-6 [doi]
• Hybrid Ring Generators for In-System Test ApplicationsJanusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak. 1-6 [doi]
• Global Tuning for System Performance Optimization of RF MIMO RadarsFerhat Can Ataman, Muslum Emir Avci, Y. B. Chethan Kumar, Sule Ozev. 1-4 [doi]
• Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-ChipGiorgio Insinga, M. Battilana, M. Coppetta, N. Mautone, G. Carnevale, M. Giltrelli, P. Scaramuzza, Rudolf Ullmann. 1-6 [doi]
• EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicSFabio Pavanello, Cédric Marchand 0002, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores, Luís Guerra e Silva, Ricardo Chaves, Luís Miguel Silveira, Mariano Ceccato, Dimitris Gizopoulos, George Papadimitriou 0001, Vasileios Karakostas, Axel Brando, Francisco J. Cazorla, Ramon Canal, Pau Closas, Adria Gusi Amigo, Paolo Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino. 1-6 [doi]
• PULP Fiction No More - Dependable PULP Systems for SpaceMarkus Ulbricht 0002, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen 0001, Francesco Conti 0001, Milos Krstic, Luca Benini. 1-10 [doi]
• Constraint-Based Automatic SBST Generation for RISC-V Processor FamiliesTobias Faller, Nikolaos Ioannis Deligiannis, Markus Schwörer, Matteo Sonza Reorda, Bernd Becker 0001. 1-6 [doi]
• Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary studyDeniz Kasap, Alessio Carpegna, Alessandro Savino, Stefano Di Carlo. 1-5 [doi]
• Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its VariantsChaofang Ma, Jianan Mu, Jing Ye 0001, Shuai Chen, Yuan Cao 0003, Huawei Li 0001, Xiaowei Li 0001. 1-6 [doi]
• Understanding Permanent Hardware Failures in Deep Learning Training Accelerator SystemsYi He, Yanjing Li. 1-6 [doi]
• Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and TechnologiesBrojogopal Sapui, Jonas Krautter, Mahta Mayahinia, Atousa Jafari, Dennis Gnad, Sergej Meschkov, Mehdi B. Tahoori. 1-6 [doi]
• Increasing SAT-Resilience of Logic Locking Mechanisms using Formal MethodsMarcel Merten, Sebastian Huhn 0001, Rolf Drechsler. 1-6 [doi]
• SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCsAthanasios Xynos, Vasileios Tenentes, Yiorgos Tsiatouhas. 1-6 [doi]
• Learn to Tune: Robust Performance Tuning in Post-Silicon ValidationPeter Domanski, Dirk Pflüger, Raphaël Latty. 1-4 [doi]
• A Survey of Recent Developments in Testability, Safety and Security of RISC-V ProcessorsJens Anders, Pablo Andreu, Bernd Becker 0001, Steffen Becker 0001, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Mathias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner 0001, Nusa Zidaric. 1-10 [doi]
• Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault SimulationFernando Fernandes dos Santos, Luigi Carro, Paolo Rech. 1-10 [doi]
• Secrets Leaking Through Quicksand: Covert Channels in Approximate ComputingLorenzo Masciullo, Roberto Passerone, Francesco Regazzoni 0001, Ilia Polian. 1-6 [doi]
• Harvesting Wasted Clock Cycles for Efficient Online TestingEslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore Manikas, Kundan Nepal. 1-6 [doi]
• Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic ModelS. L. Tweehuysen, G. L. A. Adriaans, M. Gomony. 1-4 [doi]
• Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and SuppressionKwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee. 1-6 [doi]
• BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-CellStefan Holst, Ruijun Ma, Xiaoqing Wen, Aibin Yan, Hui Xu. 1-6 [doi]
• On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSIMahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 1-4 [doi]
• Online Fault Detection and Diagnosis in RRAMMoritz Fieback, Filip Bradaric, Mottaqiallah Taouil, Said Hamdioui. 1-6 [doi]
• A Single-Event Latchup setup for high-precision AMS circuitsGildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, C. Dominguez, Maria Angeles Jalón, L. Carranza. 1-6 [doi]
• SCI-FI: a Smart, aCcurate and unIntrusive Fault-Injector for Deep Neural NetworksGabriele Gavarini, Annachiara Ruospo, Ernesto Sánchez 0001. 1-6 [doi]
• An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?Bruno E. Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis 0001, Marco Ottavi. 1-6 [doi]
• High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysisJhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen. 1-4 [doi]
• Semi-Supervised Deep Learning for Microcontroller Performance ScreeningNicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero. 1-6 [doi]
• *Shao-Chun Hung, Arjun Chaudhuri, Krishnendu Chakrabarty. 1-6 [doi]
• Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspectiveMarti Alonso, David Andreu 0003, Ramon Canal, Stefano Di Carlo, Cristiano Pegoraro Chenet, Juanjo Costa, Andreu Girones, Dimitris Gizopoulos, Vasileios Karakostas, Beatriz Otero, George Papadimitriou 0001, Eva Rodríguez, Alessandro Savino. 1-6 [doi]
• Physical-aware Interconnect Testing and Repairing of ChipletsChangming Cui, Tuanhui Xu, Haitao Fu, Junlin Huang. 1-4 [doi]
• PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock GatesUpoma Das, M. Sazadur Rahman, N. Nalla Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi. 1-6 [doi]
• High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking ApplicationsAsimina Koutra, Vasileios Tenentes. 1-6 [doi]
• Image Test Libraries for the on-line self-test of functional units in GPUs running CNNsAnnachiara Ruospo, Gabriele Gavarini, A. Porsia, Matteo Sonza Reorda, Ernesto Sánchez 0001, Riccardo Mariani, J. Aribido, Jyotika Athavale. 1-6 [doi]
• DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability AssessmentMohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin. 1-6 [doi]
• BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse EngineeringTao Zhang, Mark M. Tehranipoor, Farimah Farahmandi. 1-6 [doi]
• Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC ArchitectureL. Ammoura, Marie-Lise Flottes, Patrick Girard 0001, J.-P. Noel, Arnaud Virazel. 1-4 [doi]
• Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write ErrorsChing-Yuan Chen, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 1-4 [doi]
• A Side-Channel Attack on a Hardware Implementation of CRYSTALS-KyberYanning Ji, Ruize Wang, Kalle Ngo, Elena Dubrova, Linus Backlund. 1-5 [doi]
• FINaL: Driving High-Level Fault Injection Campaigns with Natural LanguageKhaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Görschwin Fey. 1-4 [doi]
• On Using Cell-Aware Methodology for SRAM Bit Cell TestingX. Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, G. di Pendina, Patrick Girard 0001, Arnaud Virazel. 1-4 [doi]
• SET Effects on Quasi Delay Insensitive and Synchronous CircuitsZaheer Tabassam, Andreas Steininger. 1-6 [doi]
• Learning-Based Characterization Models for Quality Assurance of Emerging Memory TechnologiesXhesila Xhafa, Patrick Girard 0001, Arnaud Virazel. 1-2 [doi]
• *Jayeeta Chaudhuri, Krishnendu Chakrabarty. 1-4 [doi]
• A Resilience Framework for Synapse Weight Errors and Firing Threshold Perturbations in RRAM Spiking Neural NetworksAnurup Saha, Chandramouli N. Amarnath, Abhijit Chatterjee. 1-4 [doi]
• Counterfeit Detection by Semiconductor Process Technology InspectionMatthias Ludwig 0005, Ann-Christin Bette, Bernhard Lippmann, Georg Sigl. 1-4 [doi]