Using High-Level Synthesis to model System Verilog procedural timing controls - researchr publication

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Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo 0002. Using High-Level Synthesis to model System Verilog procedural timing controls. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. pages 1-6, IEEE, 2023. [doi]

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