Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo 0002. Using High-Level Synthesis to model System Verilog procedural timing controls. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. pages 1-6, IEEE, 2023. [doi]
@inproceedings{PozzoniFMPP23,
title = {Using High-Level Synthesis to model System Verilog procedural timing controls},
author = {Luca Ezio Pozzoni and Fabrizio Ferrandi and Loris Mendola and Alfio Antonino Palazzo and Francesco Pappalardo 0002},
year = {2023},
doi = {10.23919/DATE56975.2023.10136907},
url = {https://doi.org/10.23919/DATE56975.2023.10136907},
researchr = {https://researchr.org/publication/PozzoniFMPP23},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023},
publisher = {IEEE},
isbn = {978-3-9819263-7-8},
}