Table of Contents

• SoftHV: a HW/SW co-designed processor with horizontal and vertical fusionAbhishek Deb, Josep M. Codina, Antonio González. 1 [doi]
• Efficient stack distance computation for priority replacement policiesGianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik. 2 [doi]
• Elastic pipeline: addressing GPU on-chip shared memory bank conflictsChunyang Gou, Georgi Gaydadjiev. 3 [doi]
• Pruning hardware evaluation space via correlation-driven application similarity analysisRosario Cammarota, Arun Kejariwal, Paolo D Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, Alexandru Nicolau. 4 [doi]
• BarrierWatch: characterizing multithreaded workloads across and within program-defined epochsSocrates Demetriades, Sangyeun Cho. 5 [doi]
• Scaling scientific applications on clusters of hybrid multicore/GPU nodesLingyuan Wang, Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Ghazawi. 6 [doi]
• Performance optimization by dynamic code transformationJosef Weidendorfer, Tilman Küstner, Sally A. McKee. 7 [doi]
• Increasing power/performance resource efficiency on virtualized enterprise serversEmmanuel Arzuaga, David R. Kaeli. 8 [doi]
• A reconfigurable cache architecture for energy efficiencyKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. 9 [doi]
• Manycore work stealingKarl-Filip Faxén, John Ardelius. 10 [doi]
• MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processorAlessio Franceschelli, Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Martino Ruggiero, Michele Lombardi, Alessio Bonfietti, Michela Milano, Luca Benini. 11 [doi]
• Hybrid high-performance low-power and ultra-low energy reliable cachesBojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero. 12 [doi]
• Dynamic co-management of persistent RAM main memory and storage resourcesJu-Young Jung, Sangyeun Cho. 13 [doi]
• Cluster-based topologies for 3D stacked architecturesMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 14 [doi]
• Maintaining real-time synchrony on SpiNNakerSergio Davies, Alexander D. Rast, Francesco Galluppi, Steve Furber. 15 [doi]
• Universal optical multi-drop bus for heterogeneous memory architectureAtsuya Okazaki, Yasunao Katayama, Seiji Munetoh. 16 [doi]
• Quantitative analysis of parallelism and data movement properties across the Berkeley computational motifsVictoria Caparrós Cabezas, Phillip Stanley-Marbell. 17 [doi]
• CnC-Hadoop: a graphical coordination language for distributed multiscale parallelismRiyaz Haque, David M. Peixotto, Vivek Sarkar. 18 [doi]
• Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmabilityFrancesca Palumbo, Danilo Pani, Andrea Deidda, Luigi Raffo. 19 [doi]
• An MPSoC design approach for multiple use-cases of throughput constrainted applicationsAhsan Shabbir, Sander Stuijk, Akash Kumar, Henk Corporaal, Bart Mesman. 20 [doi]
• AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designsGuilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang 0003. 21 [doi]
• A parallel programming framework orchestrating multiple languages and architecturesMasana Murase, Hideaki Komatsu, Kumiko Maeda, Shigeho Noda, Munehiro Doi, Ryutaro Himeno. 22 [doi]
• Composable local memory organisation for streaming applications on embedded MPSoCsJude Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink. 23 [doi]
• Rematerialization-based register allocation through reverse computingMouad Bahi, Christine Eisenbeis. 24 [doi]
• On-the-fly detection of precise loop nests across procedures on a dynamic binary translation systemYukinori Sato, Yasushi Inoguchi, Tadao Nakamura. 25 [doi]
• Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architectureGuilherme Ottoni, Thomas Hartin, Christopher T. Weaver, Jason Brandt, Belliappa Kuttanna, Hong Wang. 26 [doi]
• Bounding the effect of partition camping in GPU kernelsAshwin M. Aji, Mayank Daga, Wu-chun Feng. 27 [doi]
• Leveraging data-structure semantics for efficient algorithmic parallelismRomain Cledat, Kaushik Ravichandran, Santosh Pande. 28 [doi]
• Multi- and many-core data mining with adaptive sparse gridsAlexander Heinecke, Dirk Pflüger. 29 [doi]
• Understanding stencil code performance on multicore architecturesFaizur Rahman, Qing Yi, Apan Qasem. 30 [doi]
• Parametrizing multicore architectures for multiple sequence alignmentSebastian Isaza, Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Georgi Gaydadjiev. 31 [doi]
• Performance analysis and optimization of molecular dynamics simulation on ::::Godson-T:::: many-core processorLiu Peng, Aiichiro Nakano, Guangming Tan, Priya Vashishta, Dongrui Fan, Hao Zhang, Rajiv K. Kalia, Fenglong Song. 32 [doi]
• Performing bitwise logic operations in cache using spintronics-based magnetic tunnel junctionsShruti Patil, David J. Lilja. 33 [doi]
• Virtual base station pool: towards a wireless network cloud for radio access networksZhenbo Zhu, Parul Gupta, Qing Wang, Shivkumar Kalyanaraman, Yonghua Lin, Hubertus Franke. 34 [doi]
• FACT: a framework for adaptive contention-aware thread migrationsKishore Kumar Pusukuri, David Vengerov, Alexandra Fedorova, Vana Kalogeraki. 35 [doi]
• Tolerating correlated failures for generalized Cartesian distributions via bipartite matchingNawab Ali, Sriram Krishnamoorthy, Mahantesh Halappanavar, Jeff Daily. 36 [doi]
• SIFT: a low-overhead dynamic information flow tracking architecture for SMT processorsMeltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri. 37 [doi]
• Scalable memory registration for high performance networks using helper threadsDong Li, Kirk W. Cameron, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz. 38 [doi]
• A flexible approach to efficient resource sharing in virtualized environmentsHui Wang, Peter Varman. 39 [doi]
• Evaluation of dynamic voltage and frequency scaling for stream programsArun Rangasamy, Y. N. Srikant. 40 [doi]