Table of Contents

• The Accelerator Wall: Limits of Chip SpecializationAdi Fuchs, David Wentzlaff. 1-14 [doi]
• Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT CoresArtemiy Margaritov, Siddharth Gupta, Rekai González-Alberquilla, Boris Grot. 15-27 [doi]
• CIDR: A Cost-Effective In-Line Data Reduction System for Terabit-Per-Second Scale SSD ArraysMohammadamin Ajdari, Pyeongsu Park, Joonsung Kim, Dongup Kwon, Jangwoo Kim. 28-41 [doi]
• Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISAAshish Venkat, Harsha Basavaraj, Dean M. Tullsen. 42-55 [doi]
• HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator ArrayLinghao Song, Jiachen Mao, Youwei Zhuo, Xuehai Qian, Hai Li 0001, Yiran Chen. 56-68 [doi]
• E-RNN: Design Optimization for Efficient Recurrent Neural Networks in FPGAsZhe Li 0001, Caiwen Ding, Siyue Wang, Wujie Wen, Youwei Zhuo, Chang Liu, Qinru Qiu, Wenyao Xu, Xue Lin, Xuehai Qian, Yanzhi Wang. 69-80 [doi]
• Bit Prudent In-Cache Acceleration of Deep Convolutional Neural NetworksXiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das. 81-93 [doi]
• Shortcut Mining: Exploiting Cross-Layer Shortcut Reuse in DCNN AcceleratorsArash AziziMazreah, Lizhong Chen. 94-105 [doi]
• Fine-Tuning the Active Timing Margin (ATM) Control Loop for Maximizing Multi-core Efficiency on an IBM POWER ServerYazhou Zu, Daniel Richins, Charles Lefurgy, Vijay Janapa Reddi. 106-119 [doi]
• μDPM: Dynamic Power Management for the Microsecond EraChih-Hsun Chou, Laxmi N. Bhuyan, Daniel Wong 0001. 120-132 [doi]
• Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUsGeorge Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos. 133-146 [doi]
• Resilient Low Voltage Accelerators for High Energy EfficiencyNandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose. 147-158 [doi]
• Pliant: Leveraging Approximation to Improve Datacenter Resource EfficiencyNeeraj Kulkarni, Feng Qi 0003, Christina Delimitrou. 159-171 [doi]
• Kelp: QoS for Accelerated Machine Learning SystemsHaishan Zhu, David Lo 0003, Liqun Cheng, Rama Govindaraju, Parthasarathy Ranganathan, Mattan Erez. 172-184 [doi]
• Enhancing Server Efficiency in the Face of Killer MicrosecondsAmirhossein Mirhosseini, Akshitha Sriraman, Thomas F. Wenisch. 185-198 [doi]
• Poly: Efficient Heterogeneous System and Application Management for Interactive ApplicationsShuo Wang, Yun Liang 0001, Wei Zhang. 199-210 [doi]
• The What's Next Intermittent Computing ArchitectureKarthik Ganesan, Joshua San Miguel, Natalie D. Enright Jerger. 211-223 [doi]
• eQASM: An Executable Quantum Instruction Set ArchitectureXiang Fu, L. Riesebos, M. A. Rol, Jeroen van Straten, J. van Someren, Nader Khammassi, Imran Ashraf, R. F. L. Vermeulen, V. Newsum, K. K. L. Loh, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, L. DiCarlo, Koen Bertels. 224-237 [doi]
• Reliability Evaluation of Mixed-Precision ArchitecturesFernando Fernandes dos Santos, Caio B. Lunardi, Daniel A. G. de Oliveira, Fabiano Libano, Paolo Rech. 238-249 [doi]
• Architecting Waferscale Processors - A GPU Case StudySaptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar 0002. 250-263 [doi]
• Conditional Speculation: An Effective Approach to Safeguard Out-of-Order Execution Against Spectre AttacksPeinan Li, Lutan Zhao, Rui Hou, Lixin Zhang 0002, Dan Meng. 264-276 [doi]
• FPGA Accelerated INDEL Realignment in the CloudLisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanovic, David A. Patterson, Anthony D. Joseph. 277-290 [doi]
• POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management VulnerabilitiesS. Karen Khatamifard, Longfei Wang, Amitabh Das, Selçuk Köse, Ulya R. Karpuzcu. 291-303 [doi]
• Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBISTShrikanth Ganapathy, John Kalamatianos, Bradford M. Beckmann, Steven Raasch, Lukasz G. Szafaryn. 304-316 [doi]
• Gables: A Roofline Model for Mobile SoCsMark Hill, Vijay Janapa Reddi. 317-330 [doi]
• Machine Learning at Facebook: Understanding Inference at the EdgeCarole-Jean Wu, David Brooks 0001, Kevin Chen, Douglas Chen, Sy Choudhury, Marat Dukhan, Kim M. Hazelwood, Eldad Isaac, Yangqing Jia, Bill Jia, Tommer Leyvand, Hao Lu, Yang Lu, Lin Qiao, Brandon Reagen, Joe Spisak, Fei Sun, Andrew Tulloch, Peter Vajda, Xiaodong Wang, Yanghan Wang, Bram Wasti, Yiming Wu, Ran Xian, Sungjoo Yoo, Peizhao Zhang. 331-344 [doi]
• VIP: A Versatile Inference ProcessorSkand Hurkat, José F. Martínez. 345-358 [doi]
• Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High SpeedupYatish Turakhia, Sneha D. Goenka, Gill Bejerano, William J. Dally. 359-372 [doi]
• Analysis and Optimization of the Memory Hierarchy for Graph Processing WorkloadsAbanti Basak, Shuangchen Li, Xing Hu, Sang Min Oh, Xinfeng Xie, Li Zhao, Xiaowei Jiang, Yuan Xie 0001. 373-386 [doi]
• FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted DataSujoy Sinha Roy, Furkan Turan, Kimmo Järvinen 0001, Frederik Vercauteren, Ingrid Verbauwhede. 387-398 [doi]
• Bingo Spatial Data PrefetcherMohammad Bakhshalipour, Mehran Shakerinava, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad. 399-411 [doi]
• NoMap: Speeding-Up JavaScript Using Hardware Transactional MemoryThomas Shull, Jiho Choi, María Jesús Garzarán, Josep Torrellas. 412-425 [doi]
• FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access OverheadsJie Zhang 0048, Myoungsoo Jung, Mahmut T. Kandemir. 426-439 [doi]
• Featherlight Reuse-Distance MeasurementQingsen Wang, Xu Liu 0001, Milind Chabbi. 440-453 [doi]
• Efficient Load Value Prediction Using Multiple Predictors and FiltersRami Sheikh, Derek Hower. 454-465 [doi]
• BRB: Mitigating Branch Predictor Side-ChannelsIlias Vougioukas, Nikos Nikoleris, Andreas Sandberg, Stephan Diestelhorst, Bashir M. Al-Hashimi, Geoff V. Merrett. 466-477 [doi]
• Elastic Instruction FetchingArthur Perais, Rami Sheikh, Luke Yen, Michael McIlvaine, Robert D. Clancy. 478-490 [doi]
• The Best of IEEE Computer Architecture Letters in 2018Paul Gratz. 491 [doi]
• Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine LearningSaumay Dublish, Vijay Nagarajan, Nigel P. Topham. 492-505 [doi]
• A Hybrid Framework for Fast and Accurate GPU Performance Estimation through Source-Level Analysis and Trace-Based SimulationXiebing Wang, Kai Huang 0001, Alois Knoll, Xuehai Qian. 506-518 [doi]
• Understanding the Future of Energy Efficiency in Multi-Module GPUsAkhil Arunkumar, Evgeny Bolotin, David W. Nellans, Carole-Jean Wu. 519-532 [doi]
• R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead ArchitecturesSushant Kondguli, Michael Huang. 533-544 [doi]
• Recycling Data Slack in Out-of-Order CoresGokul Subramanian Ravi, Mikko H. Lipasti. 545-557 [doi]
• Freeway: Maximizing MLP for Slice-Out-of-Order ExecutionRakesh Kumar 0003, Mehdi Alipour, David Black-Schaffer. 558-569 [doi]
• Enabling Transparent Memory-Compression for Commodity Memory SystemsVinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi. 570-581 [doi]
• D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High ThroughputJeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa, Onur Mutlu. 582-595 [doi]
• PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory SystemsApostolos Kokolis, Dimitrios Skarlatos, Josep Torrellas. 596-608 [doi]
• PIM-VR: Erasing Motion Anomalies In Highly-Interactive Virtual Reality World with Customized Memory CubeChenhao Xie, Xingyao Zhang, Ang Li, Xin Fu, Shuaiwen Song. 609-622 [doi]
• Rendering Elimination: Early Discard of Redundant Tiles in the Graphics PipelineMarti Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Pedro Marcuello, Antonio González 0001. 623-634 [doi]
• Early Visibility Resolution for Removing Ineffectual Computations in the Graphics PipelineMarti Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González 0001. 635-646 [doi]
• String Figure: A Scalable and Elastic Memory Network ArchitectureMatheus Ogleari, Ye Yu, Chen Qian, Ethan L. Miller, Jishen Zhao. 647-660 [doi]
• NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural NetworksHyeonuk Kim, Jaehyeong Sim, YeongJae Choi, Lee-Sup Kim. 661-673 [doi]
• Active-Routing: Compute on the Way for Near-Data ProcessingJiayi Huang, Ramprakash Reddy Puli, Pritam Majumder, Sungkeun Kim, Rahul Boyapati, Ki Hwan Yum, Eun Jung Kim 0001. 674-686 [doi]
• Understanding the Impact of Socket Density in Density Optimized ServersManish Arora, Matt Skach, Wei Huang 0004, Xudong An, Jason Mars, Lingjia Tang, Dean M. Tullsen. 687-700 [doi]
• A Scalable Priority-Aware Approach to Managing Data Center Server PowerYang Li, Charles R. Lefurgy, Karthick Rajamani, Malcolm S. Allen-Ware, Guillermo J. Silva, Daniel D. Heimsoth, Saugata Ghose, Onur Mutlu. 701-714 [doi]
• Power Aware Heterogeneous Node AssemblyBilge Acun, Alper Buyuktosunoglu, Eun-Kyung Lee, Yoonho Park. 715-727 [doi]