Yazhou Zu, Daniel Richins, Charles Lefurgy, Vijay Janapa Reddi. Fine-Tuning the Active Timing Margin (ATM) Control Loop for Maximizing Multi-core Efficiency on an IBM POWER Server. In 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, Washington, DC, USA, February 16-20, 2019. pages 106-119, IEEE, 2019. [doi]
Abstract is missing.