Table of Contents

• Biologically-inspired massively-parallel architectures - Computing beyond a million processorsStephen B. Furber. 1 [doi]
• VESPA: Variability emulation for System-on-Chip performance analysisVivek J. Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey. 2-7 [doi]
• Thermal-aware on-line task allocation for 3D multi-core processor throughput optimizationChiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang. 8-13 [doi]
• An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systemsYi Wang 0003, Duo Liu, Zhiwei Qin, Zili Shao. 14-19 [doi]
• Register allocation for simultaneous reduction of energy and peak temperature on registersTiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li. 20-25 [doi]
• A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodelsL. Gobbato, Alessandro Chinea, Stefano Grivet-Talocia. 26-31 [doi]
• Fast statistical analysis of RC nets subject to manufacturing variabilitiesYu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luis Miguel Silveira, Nick van der Meijs. 31-37 [doi]
• A scaled random walk solver for fast power grid analysisBaktash Boghrati, Sachin S. Sapatnekar. 38-43 [doi]
• A block-diagonal structured model reduction scheme for power grid networksZheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong. 44-49 [doi]
• Logic synthesis and physical design: Quo vadis?Giovanni De Micheli. 50 [doi]
• Panel and embedded tutorial - Logic synthesis and place and route: After 20 years of engagement, wedding in view?Marco Casale-Rossi, Antun Domic. 51 [doi]
• Time redundant parity for low-cost transient error detectionDavid J. Palframan, Nam Sung Kim, Mikko H. Lipasti. 52-57 [doi]
• Cross-layer optimized placement and routing for FPGA soft error mitigationKeheng Huang, Yu Hu, Xiaowei Li 0001. 58-63 [doi]
• Trigonometric method to handle realistic error probabilities in logic circuitsChien-Chih Yu, John P. Hayes. 64-69 [doi]
• Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori. 70-75 [doi]
• FlexRay switch scheduling - A networking concept for electric vehiclesMartin Lukasiewycz, Samarjit Chakraborty, Paul Milbredt. 76-81 [doi]
• A reconfiguration approach for fault-tolerant FlexRay networksKay Klobedanz, Andreas Koenig, Wolfgang Müller 0003. 82-87 [doi]
• Simplified programming of faulty sensor networks via code transformation and run-time interval computationLan S. Bai, Robert P. Dick, Peter A. Dinda, Pai H. Chou. 88-93 [doi]
• Parallel accelerators for GlimmerHMM bioinformatics algorithmNafsika Chrysanthou, Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou. 94-99 [doi]
• An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platformsFrancesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini. 100-105 [doi]
• Sub-clock power-gating technique for minimising leakage power during active modeJatin N. Mistry, Bashir M. Al-Hashimi, David Flynn, Stephen Hill. 106-111 [doi]
• An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP)Andreas Kern, Thilo Streichert, Jürgen Teich. 112-117 [doi]
• Formal specification and systematic model-driven testing of embedded automotive systemsSebastian Siegl, Kai-Steffen Jens Hielscher, Reinhard German, Christian Berger. 118-123 [doi]
• Embedded tutorial: Addressing critical power management verification issues in low power designsBhanu Kapoor, Knut M. Just. 124 [doi]
• Topologically homogeneous power-performance heterogeneous multicore systemsKoushik Chakraborty, Sanghamitra Roy. 125-130 [doi]
• Variability-aware duty cycle scheduling in long running embedded sensing systemsLucas Francisco Wanner, Rahul Balani, Sadaf Zahedi, Charwak Apte, Puneet Gupta, Mani B. Srivastava. 131-136 [doi]
• Reliability-aware thermal management for hard real-time applications on multi-core processorsVinay Hanumaiah, Sarma B. K. Vrudhula. 137-142 [doi]
• Clause simplification through dominator analysisHyoJung Han, HoonSang Jin, Fabio Somenzi. 143-148 [doi]
• Integration of orthogonal QBF solving techniquesSven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker. 149-154 [doi]
• STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebraEvgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel. 155-160 [doi]
• Empirical design bugs prediction for verificationQi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Yue Wu, Weiwu Hu. 161-166 [doi]
• Decision ordering based property decomposition for functional test generationMingsong Chen, Prabhat Mishra. 167-172 [doi]
• Towards coverage closure: Using GoldMine assertions for generating design validation stimulusLingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan. 173-178 [doi]
• Scalable hybrid verification for embedded softwareJörg Behrend, Djones Lettnin, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel. 179-184 [doi]
• Diagnosing scan chain timing faults through statistical feature analysis of scan imagesMingjing Chen, Alex Orailoglu. 185-190 [doi]
• Design-for-test methodology for non-scan at-speed testingMainak Banga, Nikhil P. Rahagude, Michael S. Hsiao. 191-196 [doi]
• A clock-gating based capture power droop reduction methodology for at-speed scan testingBo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu. 197-203 [doi]
• Pruning infeasible paths for tight WCRT analysis of synchronous programsSidharta Andalam, Partha S. Roop, Alain Girault. 204-209 [doi]
• Fast and accurate resource conflict simulation for performance analysis of multi-core systemsStefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel. 210-215 [doi]
• An approach to improve accuracy of source-level TLMs of embedded softwareZhonglei Wang, Kun Lu, Andreas Herkersdorf. 216-221 [doi]
• Host-compiled multicore RTOS simulator for embedded real-time software developmentParisa Razaghi, Andreas Gerstlauer. 222-227 [doi]
• A flexible high throughput multi-ASIP architecture for LDPC and turbo decodingPurushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel. 228-233 [doi]
• A low-power VLIW processor for 3GPP-LTE complex numbers processingChristian Bernard, Fabien Clermidy. 234-239 [doi]
• +-Best detectorNils Heidmann, Till Wiegand, Steffen Paul. 240-245 [doi]
• An energy-efficient 64-QAM MIMO detector for emerging wireless standardsNariman Moezzi Madani, Thorlindur Thorolfsson, Joseph Crop, Patrick Chiang, W. Rhett Davis. 246-251 [doi]
• Beyond UPF & CPF: Low-power design and verificationBarry M. Pangrle, John Biggs, C. Clavel, Olivier Domerego, Knut M. Just. 252 [doi]
• Buffering implications for the design space of streaming MEMS storageMohammed G. Khatib, Leon Abelmann. 253-256 [doi]
• Efficient RC power grid verification using node eliminationAnkit Goyal, Farid N. Najm. 257-260 [doi]
• A novel TSV topology for many-tier 3D power-delivery networksMichael B. Healy, Sung Kyu Lim. 261-264 [doi]
• Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memoriesNor Zaidi Haron, Said Hamdioui. 265-268 [doi]
• DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systemsTobias Ziermann, Jürgen Teich, Zoran Salcic. 269-272 [doi]
• A sensor fusion algorithm for an integrated angular position estimation with inertial measurement unitsSimone Sabatelli, Francesco Sechi, Luca Fanucci, Alessandro Rocchi. 273-276 [doi]
• Speeding-up SIMD instructions dynamic binary translation in embedded processor simulationLuc Michel, Nicolas Fournel, Frédéric Pétrot. 277-280 [doi]
• System-level energy-efficient scheduling for hard real-time embedded systemsLinwei Niu. 281-284 [doi]
• Timing error statistics for energy-efficient robust DSP systemsRami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag. 285-288 [doi]
• Enabling improved power management in multicore processors through clustered DVFST. Kolpe, Antonia Zhai, Sachin S. Sapatnekar. 293-298 [doi]
• ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applicationsMojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi. 298-292 [doi]
• Dynamic thermal management in 3D multi-core architecture through run-time adaptationFazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel. 299-304 [doi]
• Distributed hardware matcher framework for SoC survivabilityIlya Wagner, Shih-Lien Lu. 305-310 [doi]
• A cost-effective substantial-impact-filter based method to tolerate voltage emergenciesSongjun Pan, Yu Hu, Xing Hu, Xiaowei Li 0001. 311-315 [doi]
• Interpolation sequences revisitedGianpiero Cabodi, Sergio Nocco, Stefano Quer. 316-322 [doi]
• Automated debugging of SystemVerilog assertionsBrian Keng, Sean Safarpour, Andreas G. Veneris. 323-328 [doi]
• Counterexample-guided SMT-driven optimal buffer sizingBryan A. Brady, Daniel E. Holcomb, Sanjit A. Seshia. 329-334 [doi]
• DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive schedulingPeng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay. 335-340 [doi]
• Cycle-count-accurate processor modeling for fast and accurate system-level simulationChen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay. 341-346 [doi]
• A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systemsCheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay. 347-352 [doi]
• Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking MethodYu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin. 353-358 [doi]
• An all-digital built-in self-test technique for transfer function characterization of RF PLLsPing-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng. 359-364 [doi]
• A true power detector for RF PA built-in calibration and testingPedro Fonseca da Mota, José Machado da Silva. 365-370 [doi]
• Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial exampleHamidreza Hashempour, Jos Dohmen, Bratislav Tasic, Bram Kruseman, Camelia Hora, Maikel van Beurden, Yizi Xing. 371-376 [doi]
• Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping"Mohit Singh, Mahendra Sakare, Shalabh Gupta. 377-382 [doi]
• Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variationsDa-Cheng Juan, Siddharth Garg, Diana Marculescu. 383-388 [doi]
• Design space exploration for 3D-stacked DRAMsChristian Weis, Norbert Wehn, Igor Loi, Luca Benini. 389-394 [doi]
• Analytical heat transfer model for thermal through-silicon viasHu Xu, Vasilis F. Pavlidis, Giovanni De Micheli. 395-400 [doi]
• A new architecture for power network in 3D ICHsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang. 401-406 [doi]
• Achieving composability in NoC-based MPSoCs through QoS management at software levelEverton Carara, Gabriel Marchesan Almeida, Gilles Sassatelli, Fernando Gehm Moraes. 407-412 [doi]
• Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point linksMarjan Asadinia, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad. 413-418 [doi]
• Guaranteed service virtual channel allocation in NoCs for run-time task schedulingMarkus Winter 0002, Gerhard Fettweis. 419-424 [doi]
• An FPGA bridge preserving traffic quality of service for on-chip network-based systemsAshkan Beyranvand Nejad, Matias Escudero Martinez, Kees Goossens. 425-430 [doi]
• Entering the path towards terabit/s wireless linksGerhard Fettweis, Falko Guderian, Stefan Krone. 431-436 [doi]
• Smart imagers of the futureAntoine Dupret, Michaël Tchagaspanian, Arnaud Verdant, Laurent Alacoque, Arnaud Peizerat. 437-442 [doi]
• Power-driven global routing for multi-supply voltage domainsTai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth. 443-448 [doi]
• Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidanceJin-Tai Yan, Zhi-Wei Chen. 449-454 [doi]
• Steiner tree based rotary clock routing with bounded skew and capacitive load balancingJianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin. 455-460 [doi]
• On routing fixed escaped boundary pins for high speed boardsTsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani. 461-466 [doi]
• Dynamic write limited minimum operating voltage for nanoscale SRAMsSatyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun. 467-472 [doi]
• Variation aware dynamic power management for chip multiprocessor architecturesMohammad Ghasemazar, Massoud Pedram. 473-478 [doi]
• Leakage aware energy minimization for real-time systems under the maximum temperature constraintHuang Huang, Gang Quan. 479-484 [doi]
• Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architecturesAnita Tino, Gul N. Khan. 485-490 [doi]
• A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clustersAbbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini. 491-496 [doi]
• Run-time deadlock detection in networks-on-chip using coupled transitive closure networksRa'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi. 497-502 [doi]
• Developing an integrated verification and debug methodologyA. Matsuda, T. Ishihara. 503-504 [doi]
• An analytical compact model for estimation of stress in multiple Through-Silicon Via configurationsGeert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas. 505-506 [doi]
• Power management verification experiences in Wireless SoCsB. Kapoor, A. Hunter, P. Tiwari. 507-508 [doi]
• Challenges in designing high speed memory subsystem for mobile applicationsTsunwai Gary Yip, Philip Yeung, Ming Li, Deborah Dressler. 509-510 [doi]
• Solid state photodetectors for nuclear medical imaging applicationsM. Mazzillo, P. G. Fallica, E. Ficarra, A. Messina, M. Romeo, Roberto Zafalon. 511-512 [doi]
• Fault grading of software-based self-test procedures for dependable automotive applicationsPaolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Oscar Ballan. 513-514 [doi]
• CARAT: Context-aware runtime adaptive task migration for multi core architecturesJanmartin Jahn, Mohammad Abdullah Al Faruque, Jörg Henkel. 515-520 [doi]
• Demand code paging for NAND flash in MMU-less embedded systemsJosé Baiocchi, Bruce R. Childers. 517-532 [doi]
• A rule-based static dataflow clustering algorithm for efficient embedded software synthesisJoachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich. 521-526 [doi]
• Architectures for online error detection and recovery in multicore processorsDimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, A. Biswas, Xavier Vera. 533-538 [doi]
• An energy-efficient 3D CMP design with fine-grained voltage scalingJishen Zhao, Xiangyu Dong, Yuan Xie. 539-542 [doi]
• Optimized model checking of multiple propertiesGianpiero Cabodi, Sergio Nocco. 543-546 [doi]
• A new distributed event-driven gate-level HDL simulation by accurate predictionDusung Kim, Maciej J. Ciesielski, Seiyang Yang. 547-550 [doi]
• Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management systemLakshmanan Balasubramanian, Puneet Sabbarwal, R. K. Mittal, Prakash Narayanan, R. K. Dash, A. D. Kudari, S. Manian, S. Polarouthu, Harikrishna Parthasarathy, R. C. Vijayaraghavan, S. Turkewadikar. 551-554 [doi]
• A 3D reconfigurable platform for 4G telecom applicationsWalid Lafi, Didier Lattard, Ahmed Amine Jerraya. 555-558 [doi]
• An LOCV-based static timing analysis considering spatial correlations of power supply variationsS. Kobayashi, K. Horiuchi. 559-562 [doi]
• Compiling SyncCharts to Synchronous CClaus Traulsen, T. Amende, Reinhard von Hanxleden. 563-566 [doi]
• Optimization of stateful hardware acceleration in hybrid architecturesXiaotao Chang, Yike Ma, Hubertus Franke, Kun Wang, Rui Hou, Hao Yu, Terry Nelms. 567-570 [doi]
• Formal reset recovery slack calculation at the register transfer levelChih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo. 571-574 [doi]
• Multi-granularity thermal evaluation of 3D MPSoC architecturesAlain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu, El Mostapha Aboulhamid, Ian O'Connor. 575-578 [doi]
• Two methods for 24 Gbps test signal synthesisDavid C. Keezer, Carl Edward Gray. 579-582 [doi]
• 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layersYi-Chung Chen, Hai Li, Yiran Chen, Robinson E. Pino. 583-586 [doi]
• Architectural exploration of 3D FPGAs towards a better balance between area and delayChia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang. 587-590 [doi]
• NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCsJoel Porquet, Alain Greiner, Christian Schwarz. 591-594 [doi]
• Low-power smart industrial controlAttila Bilgic, Vincent Pichot, Michael Gerding, Felix Bruns. 595-599 [doi]
• Low power interconnects for SIMD computersMark Woh, Sudhir Satpathy, Ronald G. Dreslinski, Danny Kershaw, Dennis Sylvester, David Blaauw, Trevor N. Mudge. 600-605 [doi]
• Wireless innovations for smartphonesHannu Kauppinen. 606 [doi]
• Flow-based partitioning and position constraints in VLSI placementMarkus Struzyna. 607-612 [doi]
• Integrated circuit white space redistribution for temperature optimizationYuankai Chen, Hai Zhou, Robert P. Dick. 613-618 [doi]
• Timing-constrained I/O buffer placement for flip-chip designsZhi-Wei Chen, Jin-Tai Yan. 619-624 [doi]
• Floorplanning exploration and performance evaluation of a new Network-on-ChipLicheng Xue, Weixing Ji, Qi Zuo, Yang Zhang. 625-630 [doi]
• Worst-case temperature analysis for real-time systemsDevendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele. 631-636 [doi]
• Black-box leakage power modeling for cell library and SRAM compilerChun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan Chien Fang, Ji-Jan Chen. 637-642 [doi]
• Clock gating optimization with delay-matchingShih-Jung Hsu, Rung-Bin Lin. 643-648 [doi]
• A low complexity stopping criterion for reducing power consumption in turbo decodersPallavi Reddy, Fabien Clermidy, Amer Baghdadi, Michel Jézéquel. 649-654 [doi]
• A novel tag access scheme for low power L2 cacheHyunsun Park, Sungjoo Yoo, Sunggu Lee. 655-660 [doi]
• Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architectureAlessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi. 661-666 [doi]
• ReliNoC: A reliable network for priority-based on-chip communicationMohammad Reza Kakoee, Valeria Bertacco, Luca Benini. 667-672 [doi]
• FARM: Fault-aware resource management in NoC-based multiprocessor platformsChen-Ling Chou, Radu Marculescu. 673-678 [doi]
• On diagnosis of multiple faults using compacted responsesJing Ye, Yu Hu, Xiaowei Li 0001. 679-684 [doi]
• On multiplexed signal tracing for post-silicon debugXiao Liu, Qiang Xu. 685-690 [doi]
• Eliminating data invalidation in debugging multiple-clock chipsJianliang Gao, Yinhe Han, Xiaowei Li 0001. 691-696 [doi]
• Parallelization of while loops in nested loop programs for shared-memory multiprocessor systemsStefan J. Geuns, Marco Jan Gerrit Bekooij, Tjerk Bijlsma, Henk Corporaal. 697-702 [doi]
• Gemma in April: A matrix-like parallel programming architecture on OpenCLTianji Wu, Di Wu, Yu Wang 0002, Xiaorui Zhang, Hong Luo, Ningyi Xu, Huazhong Yang. 703-708 [doi]
• Evaluating the potential of graphics processors for high performance embedded computingShuai Mu, Chenxi Wang, Ming Liu, Dongdong Li, Maohua Zhu, Xiaoliang Chen, Xiang Xie, Yangdong Deng. 709-714 [doi]
• Virtual Manycore platforms: Moving towards 100+ processor coresRainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen. 715-720 [doi]
• Embedded software debug and test: Needs and requirements for innovations in debuggingMarkus Winterholer. 721 [doi]
• Powering and communicating with mm-size implantsJan M. Rabaey, Michael Mark, David Chen, Christopher Sutardja, Chongxuan Tang, Suraj Gowda, Mark Wagner, Dan Werthimer. 722-727 [doi]
• An antenna-filter codesign for cardiac implantsEmeric de Foucauld, Jean-Baptiste David, Christophe Delaveaud, Pascal Ciais. 728-733 [doi]
• Design implications of memristor-based RRAM cross-point structuresCong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie. 734-739 [doi]
• Robust 6T Si tunneling transistor SRAM designXuebei Yang, Kartik Mohanram. 740-745 [doi]
• Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memoryJingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin Hsing-Mean Sha. 746-751 [doi]
• A new reconfigurable clock-gating technique for low power SRAM-based FPGAsLuca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar. 752-757 [doi]
• Controlled timing-error acceptance for low energy IDCT designKu He, Andreas Gerstlauer, Michael Orshansky. 758-763 [doi]
• Energy parsimonious circuit design through probabilistic pruningLingamneni Avinash, Christian C. Enz, Jean-Luc Nagel, Krishna V. Palem, Christian Piguet. 764-769 [doi]
• Stage number optimization for switched capacitor power converters in micro-scale energy harvestingChao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy. 770-775 [doi]
• Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoringNaoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu. 776-781 [doi]
• VANDAL: A tool for the design specification of nanophotonic networksGilbert Hendry, Johnnie Chan, Luca P. Carloni, Keren Bergman. 782-787 [doi]
• Optical Ring Network-on-Chip (ORNoC): Architecture and design methodologySébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin. 788-793 [doi]
• Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limitsDragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir. 794-799 [doi]
• On design of test structures for lithographic process corner identificationAswin Sreedhar, Sandip Kundu. 800-805 [doi]
• An electrical test method for MEMS convective accelerometers: Development and evaluationAhmed Amine Rekik, Florence Azaïs, Norbert Dumas, Frédérick Mailly, Pascal Nouet. 806-811 [doi]
• Correlating inline data with final test outcomes in analog/RF devicesNathan Kupp, Mustapha Slamani, Yiorgos Makris. 812-817 [doi]
• Systematic design of a programmable low-noise CMOS neural interface for cell activity recordingCarolina Mora Lopez, Silke Musa, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle. 818-823 [doi]
• A real-time compressed sensing-based personal electrocardiogram monitoring systemKarim Kanoun, Hossein Mamaghanian, Nadia Khaled, David Atienza. 824-829 [doi]
• A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicoresAndrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini. 830-835 [doi]
• An effective multi-source energy harvester for low power applicationsDavide Carli, Davide Brunelli, Luca Benini, Massimiliano Ruggeri. 836-841 [doi]
• Composing heterogeneous components for system-wide performance analysisSimon Perathoner, Kai Lampka, Lothar Thiele. 842-847 [doi]
• Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis toolsKees A. Vissers, Stephen Neuendorffer, Juanjo Noguera. 848-850 [doi]
• Architectures and modeling of predictable memory controllers for improved system integrationBenny Akesson, Kees Goossens. 851-856 [doi]
• SoC infrastructures for predictable system integrationPieter van der Wolf, Jeroen Geuzebroek. 857-862 [doi]
• Early chip planning cockpitJeonghee Shin, John A. Darringer, Guojie Luo, Alan J. Weger, C. L. Johnson. 863-866 [doi]
• Power reduction via near-optimal library-based cell-size selectionMohammad Rahman, Hiran Tennakoon, Carl Sechen. 867-870 [doi]
• Scalable packet classification via GPU metaprogrammingKang-kang, Y. S. Deng. 871-874 [doi]
• Battery-supercapacitor hybrid system for high-rate pulsed load applicationsDonghwa Shin, Younghyun Kim, Jaeam Seo, Naehyuck Chang, Yanzhi Wang, Massoud Pedram. 875-878 [doi]
• Feedback based droop mitigationSalvatore Pontarelli, Marco Ottavi, Adelio Salsano, Kamran Zarrineh. 879-882 [doi]
• A 0.964mW digital hearing aid systemPeng Qiao, Henk Corporaal, Menno Lindwer. 883-886 [doi]
• HypoEnergy. Hybrid supercapacitor-battery power-supply optimization for Energy efficiencyAzalia Mirhoseini, Farinaz Koushanfar. 887-890 [doi]
• Fine-grain OpenMP runtime support with explicit communication hardware primitivesPranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Dimitrios S. Nikolopoulos, Manolis Katevenis. 891-894 [doi]
• Transition-Time-Relation based capture-safety checking for at-speed scan test generationKohei Miyase, X. Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara. 895-898 [doi]
• 2D and 3D integration with organic and silicon electronicsClinton K. Landrock, Badr Omrane, Yindar Chuo, Bozena Kaminska, Jeydmer Aristizabal. 899-904 [doi]
• Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodesAlex S. Weddell, Geoff V. Merrett, Bashir M. Al-Hashimi. 905-908 [doi]
• A fault-tolerant deadlock-free adaptive routing for on chip interconnectsFabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis. 909-912 [doi]
• Smart devices panel session - Integrating the real world interfacesAhmed Jerraya, John Goodacre. 913 [doi]
• Re-engineering cyber-physical control applications for hybrid communication protocolsDip Goswami, Reinhard Schneider 0001, Samarjit Chakraborty. 914-919 [doi]
• Precise WCET calculation in highly variant real-time systemsPascal Montag, Sebastian Altmeyer. 920-925 [doi]
• Optimal scheduling of switched FlexRay networksThijs Schenkelaars, Bart Vermeulen, Kees Goossens. 926-931 [doi]
• On the efficacy of NBTI mitigation techniquesTuck Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar. 932-937 [doi]
• Partitioned cache architectures for reduced NBTI-induced agingAndrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino. 938-943 [doi]
• Adaptive voltage over-scaling for resilient applicationsPhilipp Klaus Krause, Ilia Polian. 944-949 [doi]
• Design of voltage-scalable meta-functions for approximate computingDebabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy. 950-955 [doi]
• MLP aware heterogeneous memory systemS. Phadke, S. Narayanasamy. 956-961 [doi]
• Impact of process variation on endurance algorithms for wear-prone memoriesAlexandre Peixoto Ferreira, Santiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé. 962-967 [doi]
• Flex memory: Exploiting and managing abundant off-chip optical bandwidthYing Wang, Lei Zhang 0008, Yinhe Han, Huawei Li, Xiaowei Li 0001. 968-973 [doi]
• Scratchpad memory optimizations for digital signal processing applicationsSyed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte. 974-979 [doi]
• Robustness analysis of 6T SRAMs in memory retention mode under PVT variationsElena I. Vatajelu, Joan Figueras. 980-985 [doi]
• Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulationBartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota, Jaume Segura. 986-991 [doi]
• Proactive recovery for BTI in high-k SRAM cellsLin Li, Youtao Zhang, Jun Yang 0002. 992-997 [doi]
• The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1Alessandro Cilardo. 998-1003 [doi]
• Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniquesOlivier Meynard, Denis Réal, Florent Flament, Sylvain Guilley, Naofumi Homma, Jean-Luc Danger. 1004-1009 [doi]
• LOEDAR: A low cost error detection and recovery scheme for ECCKun Ma, Kaijie Wu. 1010-1015 [doi]
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• Methods and tools for component-based system designJoseph Sifakis. 1022 [doi]
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• Component-based design for the futureEdward A. Lee, Alberto L. Sangiovanni-Vincentelli. 1029 [doi]
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• Wireless communication and energy harvesting in automobilesStefan Mahlknecht, Tom J. Kazmierski, Christoph Grimm, Leran Wang. 1042-1047 [doi]
• Power management trends in portable consumer applicationsJess Brown. 1048-1052 [doi]
• An efficient mask optimization method based on homotopy continuation techniqueF. Liu, Xiaokang Shi. 1053-1058 [doi]
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• Verifying dynamic aspects of UML modelsMathias Soeken, Robert Wille, Rolf Drechsler. 1077-1082 [doi]
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• A high-level analytical model for application specific CMP design explorationAndrew Cassidy, Kai Yu, Haolang Zhou, Andreas G. Andreou. 1095-1100 [doi]
• Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate modelBo Liu, Ying He, Patrick Reynaert, Georges G. E. Gielen. 1101-1106 [doi]
• A method for fast jitter tolerance analysis of high-speed PLLsStefan Erb, Wolfgang Pribyl. 1107-1112 [doi]
• SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMsKarthik V. Aadithya, Alper Demir, Sriramkumar Venugopalan, Jaijeet S. Roychowdhury. 1113-1118 [doi]
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• System-level power estimation methodology using cycle- and bit-accurate TLMMiltos D. Grammatikakis, Stratos Politis, Jean-Pierre Schoellkopf, Constantin Papadas. 1125-1126 [doi]
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• Energy-efficient scheduling of real-time tasks on cluster-based multicoresFanxin Kong, Wang Yi 0001, Qingxu Deng. 1135-1140 [doi]
• E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memoriesLuis Angel D. Bathen, Nikil D. Dutt. 1141-1146 [doi]
• Modeling manufacturing process variation for design and testSandip Kundu, Aswin Sreedhar. 1147-1152 [doi]
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• Correlating models and silicon for improved parametric yieldR. Aitken, Greg Yeric, D. Flynn. 1159-1163 [doi]
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• Improving the efficiency of a hardware transactional memory on an NoC-based MPSoCLeonardo Kunz, Gustavo Girão, F. R. Wagner. 1168-1171 [doi]
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• A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design featuresCristian Ferent, Alex Doboli. 1212-1217 [doi]
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• Energy-modulated computingAlex Yakovlev. 1340-1345 [doi]
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