Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang. Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 1584-1589, IEEE, 2011. [doi]
Abstract is missing.