Abstract is missing.
- Rethinking memory system design for data-intensive computingOnur Mutlu. [doi]
- Visual processing sparks a new class of processorsMarco Jacobs. [doi]
- Parallel program = operator + schedule + parallel data structureKeshav Pingali. [doi]
- Experiences in speeding up computer vision applications on mobile computing platformsLuna Backes, Alejandro Rico, Björn Franke. 1-8 [doi]
- Parallelism extraction in embedded software for android devicesMiguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma. 9-17 [doi]
- Improving accuracy of source level timing simulation for GPUs using a probabilistic resource modelChristoph Gerum, Wolfgang Rosenstiel, Oliver Bringmann. 18-25 [doi]
- High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centersDionysios Diamantopoulos, Christoforos Kachris. 26-33 [doi]
- Reconfigurable computing for future vision-capable devicesMiguel Bordallo López, Alejandro Nieto, Olli Silvén, Jani Boutellier, David López Vilariño. 34-41 [doi]
- Imposing coarse-grained reconfiguration to general purpose processorsMilovan Duric, Milan Stanic, Ivan Ratkovic, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero, Aaron Smith. 42-51 [doi]
- Learning-based analytical cross-platform performance predictionXinnian Zheng, Pradeep Ravikumar, Lizy K. John, Andreas Gerstlauer. 52-59 [doi]
- Bridging the semantic gap between heterogeneous modeling formalisms and FMIStavros Tripakis. 60-69 [doi]
- A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU modelsEfstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker. 70-77 [doi]
- Platform-aware dynamic data type refinement methodology for radix tree Data StructuresThomas Papastergiou, Lazaros Papadopoulos, Dimitrios Soudris. 78-85 [doi]
- FNOCEE: A framework for NoC evaluation by FPGA-based emulationDaniel Pfefferkorn, Achim Schmider, Guillermo Payá Vayá, Martin Neuenhahn, Holger Blume. 86-95 [doi]
- Framework for parameter analysis of FPGA-based image processing architecturesMarc Reichenbach, Benjamin Pfundt, Dietmar Fey. 96-102 [doi]
- Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary TranslatorTom Spink, Harry Wagstaff, Björn Franke, Nigel P. Topham. 103-112 [doi]
- Efficient distribution of Triggered Synchronous Block Diagrams on asynchronous platformsYang Yang, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli. 113-122 [doi]
- HEVC in-loop filters GPU parallelization in embedded systemsDiego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa. 123-130 [doi]
- Tervel: A unification of descriptor-based techniques for non-blocking programmingSteven D. Feldman, Pierre LaBorde, Damian Dechev. 131-140 [doi]
- Physical design aware system level synthesis of hardwareNasim Farahini, Ahmed Hemani, Hasan Sohofi, Shuo Li. 141-148 [doi]
- A high-level DRAM timing, power and area exploration toolOmar Naji, Christian Weis, Matthias Jung 0001, Norbert Wehn, Andreas Hansson. 149-156 [doi]
- Towards self-adaptive MPSoC systems with adaptivity throttlingWei Quan, Andy D. Pimentel. 157-164 [doi]
- An interval algebra for multiprocessor resource allocationLeandro Soares Indrusiak, Piotr Dziurzanski. 165-172 [doi]
- Application autotuning to support runtime adaptivity in multicore architecturesDavide Gadioli, Gianluca Palermo, Cristina Silvano. 173-180 [doi]
- Chip-independent Error Correction in main memoriesMehrtash Manoochehri, Michel Dubois. 181-188 [doi]
- Decentralized diagnosis of permanent faults in automotive E/E architecturesPeter Waszecki, Martin Lukasiewycz, Samarjit Chakraborty. 189-196 [doi]
- Hardware task migration module for improved fault tolerance and predictabilityShyamsundar Venkataraman, Rui Santos, Akash Kumar, Jasper Kuijsten. 197-202 [doi]
- Software fault tolerance for FPUs via vectorizationZhi Chen, Ryoichi Inagaki, Alexandru Nicolau, Alexander V. Veidenbaum. 203-210 [doi]
- 3D-stacked many-core architecture for biological sequence analysis problemsPei Liu, Ahmed Hemani, Kolin Paul. 211-220 [doi]
- An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithmErnst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars. 221-227 [doi]
- Dynamic re-vectorization of binary codeNabil Hallou, Erven Rohou, Philippe Clauss, Alain Ketterlin. 228-237 [doi]
- Generating ASIPs with reduced number of connections to the register-fileYosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv. 238-245 [doi]
- AEGLE: A big bio-data analytics framework for integrated health-care servicesDimitrios Soudris, Sotirios Xydis, Christos Baloukas, Anastasia Hadzidimitriou, Ioanna Chouvarda, Kostas Stamatopoulos, Nicos Maglaveras, John Chang, Andreas Raptopoulos, David Manset, Barbara K. Pierscionek, Reem Kayyali, Nada Phillip, Tobias Becker, Katerina Vaporidi, Eumorphia Kondili, Dimitrios Georgopoulos, Lesley Ann Sutton, Richard Rosenquist, Lydia Scarfo, Paolo Ghia. 246-253 [doi]
- Designing applications for heterogeneous many-core architectures with the FlexTiles PlatformBenedikt Janßen, Fynn Schwiegelshohn, Martijn Koedam, François Duhem, Leonard Masing, Stephan Werner 0002, Christophe Huriaux, Antoine Courtay, Emilie Wheatley, Kees G. W. Goossens, Fabrice Lemonnier, Philippe Millet, Jürgen Becker, Olivier Sentieys, Michael Hübner. 254-261 [doi]
- The AXIOM project (Agile, eXtensible, fast I/O Module)Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Carlos Álvarez, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Paolo Gai, Antonio Rizzo, Roberto Giorgi. 262-269 [doi]
- HARPA: Solutions for dependable performance under physically induced performance variabilityDimitrios Rodopoulos, Simone Corbetta, Giuseppe Massari, Simone Libutti, Francky Catthoor, Yiannakis Sazeides, Chrysostomos Nicopoulos, Antoni Portero, Etienne Cappe, Radim Vavrík, Vít Vondrák, Dimitrios Soudris, Federico Sassi, Agnes Fritsch, William Fornaciari. 270-277 [doi]
- Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approachCédric Ben Aoun, Liliana Andrade, Torsten Mähne, François Pêcheux, Marie-Minerve Louërat, Alain Vachoux. 278-285 [doi]
- Multi-Domain Virtual Prototyping in a SystemC SIL framework: A heating system case studyNikolaos Ilieskou, Marijn Blom, Lou J. Somers, Michel A. Reniers, Twan Basten. 286-294 [doi]
- Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-endKiki Wirianto, Amir Zjajo, Carlo Galuzzi, Rene van Leuken. 295-302 [doi]
- Power optimizations for transport triggered SIMD processorsJoonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman. 303-309 [doi]
- Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point acceleratorsJiri Kadlec. 310-314 [doi]
- Using VLIW softcore processors for image processing applicationsJoost Hoozemans, Stephan Wong, Zaid Al-Ars. 315-318 [doi]
- Current analysis approaches and performance needs for whole slide image processing in breast cancer diagnosticsIrene Pollanen, Billy Braithwaite, Keijo Haataja, Tiia Ikonen, Pekka Toivanen. 319-325 [doi]
- GPU implementation of an anisotropic Huber-L1 dense optical flow algorithm using OpenCLDuygu Buyukaydin, Toygar Akgun. 326-331 [doi]
- Performance evaluation of image noise reduction computing on a mobile platformJari Hannuksela, Matti Niskanen, Markus Turtinen. 332-337 [doi]
- Multi-Constraint multi-processor Resource AllocationAmir R. B. Behrouzian, Dip Goswami, Twan Basten, Marc Geilen, Hadi Alizadeh Ara. 338-346 [doi]
- ViPES 2015 - PrefaceDiana Göhringer, Michael Hübner, Jerónimo Castrillón, Cristina Silvano. 347 [doi]
- Deterministic event-based control of Virtual Platforms for MPSoC software debuggingLuis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid. 348-353 [doi]
- ESL power estimation using virtual platforms with black box processor modelsStefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen. 354-359 [doi]
- A framework for reducing the modeling and simulation complexity of Cyberphysical SystemsNikolaos Zompakis, Kostas Siozios. 360-365 [doi]
- A scriptable, standards-compliant reporting and logging extension for SystemCJan Wagner, Rolf Meyer, Rainer Buchty, Mladen Berekovic. 366-371 [doi]
- A lightweight infrastructure for the dynamic creation and configuration of virtual platformsChristian Sauer, Hans Peter Löb. 372-377 [doi]
- Parallel SystemC simulation for ESL design using flexible time decouplingJan Henrik Weinstock, Rainer Leupers, Gerd Ascheid. 378-383 [doi]
- A virtual platform for exploring hierarchical interconnection for many-accelerator systemsEfstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos. 384-389 [doi]
- MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCsPhilipp Wehner, Jens Rettkowski, Tobias Kleinschmidt, Diana Göhringer. 390-395 [doi]