Abstract is missing.
- VLSI Systems for Embedded VideoWayne Wolf, Burak Ozer, Tiehan Lv. 3-6 [doi]
- Optimal Supply and Threshold Scaling for Subthreshold CMOS CircuitsAlice Wang, Anantha Chandrakasan, Stephen V. Kosonocky. 7-14 [doi]
- System Design and Power Optimization for Mobile ComputersAsim Smailagic, Matthew Ettus. 15-19 [doi]
- Hardware-Software Co-Adaptation for Data-Intensive Embedded ApplicationsIsmail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. 20-25 [doi]
- A Low Power High Performance Distributed DCT ArchitectureAhmed M. Shams, Wendi Pan, Archana Chidanandan, Magdy A. Bayoumi. 26-34 [doi]
- Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area ApproachVikas Chandra, Herman Schmit. 35-40 [doi]
- Optimal Timing for Skew-Tolerant High-Speed Domino LogicSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. 41-46 [doi]
- Multi-Output Timed Shannon CircuitsMitchell A. Thornton, Rolf Drechsler, D. Michael Miller. 47-52 [doi]
- Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse ComputationAdnan Abdul-Aziz Gutub, Alexandre F. Tenca, Çetin Kaya Koç. 53-58 [doi]
- Impact of Technology Scaling in the Clock System PowerDavid Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. 59-64 [doi]
- Datapath Scheduling using Dynamic Frequency ClockingSaraju P. Mohanty, N. Ranganathan, Vamsi Krishna. 65-70 [doi]
- Temperature Variable Supply Voltage for Power ReductionKaveh Shakeri, James D. Meindl. 71-74 [doi]
- Force-Directed Scheduling for Dynamic Power OptimizationSuvodeep Gupta, Srinivas Katkoori. 75-82 [doi]
- Efficient Adder Circuits Based on a Conservative Reversible Logic GateJ. W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li. 83-88 [doi]
- Noise Tolerant Low Power Dynamic TSPCL D Flip-FlopsMohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi. 89-94 [doi]
- High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow GraphNaotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama. 95-100 [doi]
- VLSI Implementation for MAC-Level DWT ArchitectureShiuh-Rong Huang, Lan-Rong Dung. 101-106 [doi]
- Speedup of Self-Timed Digital Systems Using Early CompletionScott C. Smith. 107-116 [doi]
- A Network on Chip Architecture and Design MethodologyShashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani. 117-124 [doi]
- A High Speed Shift-Invariant Wavelet Transform Chip for Video CompressionHenry Y. H. Chuang, David P. Birch, Li-Chang Liu, Jong-Chih Chien, Steven P. Levitan, Ching-Chung Li. 125-134 [doi]
- Accelerating Retiming Under the Coupled-Edge Timing ModelIngmar Neumann, Kolja Sulimma, Wolfgang Kunz. 135-140 [doi]
- Automated Synthesis of Standard Cells using Genetic AlgorithmsAnil Bahuman, Benjamin Bishop, Khaled Rasheed. 141-150 [doi]
- Improving Structural FSM Traversal by Constraint-Satisfying Logic SimulationMarkus Wedler, Dominik Stoffel, Wolfgang Kunz. 151-158 [doi]
- An Efficient Partitioning Algorithm of Combinational CMOS CircuitsBassam Shaer, Khaled Dib. 159-164 [doi]
- A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq TestSrdjan Dragic, Martin Margala. 165-170 [doi]