Roy E. Scheuerlein - researchr alias

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Viewing Publication 1 - 5 from 5

1992

A large V/sub DS/ data retention test pattern for DRAM'sRobert L. Franch, Sang H. Dhong, Roy E. Scheuerlein. jssc, 27(8):1214-1217, August 1992. [doi]

A 14-ns 14-Mb CMOS DRAM with 300-mW active powerToshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa. jssc, 27(9):1222-1228, September 1992. [doi]

A pulsed sensing scheme with a limited bit-line swingRoy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong. jssc, 27(4):678-682, April 1992. [doi]

1989

1988

Offset word-line architecture for scaling DRAMs to the gigabit levelRoy E. Scheuerlein, James D. Meindl. jssc, 23(1):41-47, February 1988. [doi]

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