Abstract is missing.
- Silicon Adventures-Go Ahead; Be Bold!Charles L. Seitz. 2 [doi]
- Architectural Considerations for Application-Specific Counterflow PipelinesBruce R. Childers, Jack W. Davidson. 3-22 [doi]
- Architecture Design of Reconfigurable Pipelined DatapathsDarren C. Cronquist, Chris Fisher, Miguel Figueroa, Paul Franklin, Carl Ebeling. 23-41 [doi]
- A Column-based Processing Array for High-speed Digital Image ProcessingTonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta. 42-56 [doi]
- Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel ProcessorSek M. Chai, Antonio Gentile, D. Scott Wills. 57-71 [doi]
- A Throughput-On-Demand Address-Event Transmitter for Neuromorphic ChipsKwabena Boahen. 72-87 [doi]
- XXI Century Gigascale Integration (GSI) : The Interconnect ProblemJames D. Meindl. 88 [doi]
- Area-Universal Circuits with Constant SlowdownSandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci. 89-98 [doi]
- A Quantitative Approach to Nonlinear Process Design Rule ScalingSpencer M. Gold, Richard B. Brown, Bruce Bernhardt. 99-113 [doi]
- Interconnect-Dominated VLSI DesignP. Ghosh, R. Mangaser, C. Mark, K. Rose. 114-122 [doi]
- Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI CircuitsLi-Rong Zheng, Hannu Tenhunen. 123-136 [doi]
- Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient ComputingNestoras Tzartzanis, William C. Athas. 137-153 [doi]
- System-on-a-Chip VLSI - Is It Finally Really Here?Robert W. Brodersen. 154 [doi]
- Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven DesignsChing-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang. 155-169 [doi]
- Low Power Gate Resizing of Combinational Circuits by Buffer-RedistributionVijay Sundararajan, Keshab K. Parhi. 170-185 [doi]
- Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear ElementsBradley A. Minch. 186-199 [doi]
- Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino PipelinesAyoob E. Dooply, Kenneth Y. Yun. 200-214 [doi]
- Adaptive Circuits Using pFET Floating-Gate DevicesPaul E. Hasler, Bradley A. Minch, Chris Diorio. 215-231 [doi]
- VLSI Architecture: Past, Present, and FutureWilliam J. Dally, Steve Lacy. 232-241 [doi]
- Exploring Microprocessor Architectures for Gigascale IntegrationLucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl. 242-255 [doi]
- The Ultrascalar Processor-An Asymptotically Scalable Superscalar MicroarchitectureDana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath. 256-275 [doi]
- Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking ChipTimothy K. Horiuchi, Ernst Niebur. 276-290 [doi]
- A Two-Dimensional, Object-Based Analog VLSI Visual Attention SystemCharles S. Wilson, Tonia G. Morris, Stephen P. DeWeerth. 291-308 [doi]
- Multi-Chip Neuromorphic Motion ProcessingCharles M. Higgins, Christof Koch. 309-325 [doi]
- Problems and Prospects for Electrical SignalingJohn Poulton. 326 [doi]
- Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal CircuitsSudip Chakrabarti, Abhijit Chatterjee. 327-341 [doi]
- Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and TestRamakrishna Voorakaranam, Abhijit Chatterjee. 342-357 [doi]
- Who Put the Sugar in Sydney Harbor?Neil Weste. 358 [doi]
- Battery-powered, Wireless MEMS Sensors for High-Sensitivity Chemical and Biological SensingCharles L. Britton Jr., R. J. Warmack, S. F. Smith, A. L. Wintenberg, T. Thundat, G. M. Brown, W. L. Bryan, J. C. Depriest, M. N. Ericson, M. S. Emery, M. R. Moore, G. W. Turner, L. G. Clonts, R. L. Jones, T. D. Threatt, Z. Hu, James M. Rochelle. 359-368 [doi]
- MEMS-Based Capacitor Arrays for Programmable Interconnect and RF ApplicationsB. E. Duewer, J. M. Wilson, D. A. Winick, Paul D. Franzon. 369-377 [doi]