Manuel Valencia - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 17 from 17

2016

Frequency analysis of a bumblebee (Bombus impatiens) wingbeatJoaquín Santoyo, Willy Azarcoya, Manuel Valencia, Alfonso Torres, Joaquín Salas. paa, 19(2):487-493, 2016. [doi]

2014

Multidisciplinary design of suitable assistive technologies for motor disabilities in ColombiaRicardo Chavarriaga, Maria N. Hurtado, Marcela Bolanos, Jose A. Loaiza, Juan M. Mayor, Manuel Valencia, Jaime Aguilar-Zambrano. ghtc 2014: 386-391 [doi]

2013

Simulation of SU-8 Frequency-Driven Scratch Drive ActuatorsDavid Conchouso, Arpys Arevalo, David Castro, Ehab Rawashdeh, Manuel Valencia, Amir Zaher, Jurgen Kosel, Ian G. Foulds. uksim 2013: 803-808 [doi]

2007

A switching noise vision of the optimization techniques for low-power synthesisJavier Castro-Ramirez, Pilar Parra, Manuel Valencia, Antonio J. Acosta. ecctd 2007: 156-159 [doi]

Asymmetric clock driver for improved power and noise performancesJavier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta. iscas 2007: 893-896 [doi]

2005

Selective Clock-Gating for Low-Power Synchronous CountersPilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia. jolpe, 1(1):11-19, 2005. [doi]

2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate LevelC. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia. patmos 2002: 353-362 [doi]

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1Pilar Parra, Antonio J. Acosta, Manuel Valencia. patmos 2002: 448-457 [doi]

2001

Gate-level simulation of CMOS circuits using the IDDM modelManuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia. iscas 2001: 483-486 [doi]

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay modelPaulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia. date 2001: 467-471 [doi]

2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI CircuitsAntonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia. patmos 2000: 316-326 [doi]

Degradation Delay Model Extension to CMOS GatesJorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia. patmos 2000: 149-158 [doi]

1995

New CMOS VLSI linear self-timed architecturesAntonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas. async 1995: 14-23 [doi]

Modular Asynchronous Arbiter Insensitive to MetastabilityManuel Valencia, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano. TC, 44(12):1456-1461, 1995.

1993

Modeling of real bistables in VHDLAntonio J. Acosta, Angel Barriga Barros, Manuel Valencia, Manuel J. Bellido, José L. Huertas. eurodac 1993: 460-465 [doi]

A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum LatchManuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro. iscas 1993: 2019-2022

1986

Asynchronous Modular ArbiterJ. Calvo, J. I. Acha, Manuel Valencia. TC, 35(1):67-70, 1986.

Sign in or sign up to see more results.

runs on WebDSL