C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia. Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. In Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido, editors, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Volume 2451 of Lecture Notes in Computer Science, pages 353-362, Springer, 2002. [doi]
Abstract is missing.