Abstract is missing.
- Performance evaluation of asynchronous logic pipelines with data dependent processing delaysDavid A. Kearney, Neil W. Bergmann. 4-13 [doi]
- New CMOS VLSI linear self-timed architecturesAntonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas. 14-23 [doi]
- Low-latency asynchronous FIFO buffersJelio T. Yantchev, C. G. Huang, Mark B. Josephs, I. M. Nedelchev. 24-31 [doi]
- Designing an asynchronous pipeline token ring interfaceAlexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov. 32 [doi]
- VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC playerJoep L. W. Kessels. 44-52 [doi]
- Single-rail handshake circuitsAd M. G. Peeters, Kees van Berkel. 53-62 [doi]
- High-level test evaluation of asynchronous circuitsRik van de Wiel. 63-71 [doi]
- A single-rail re-implementation of a DCC error detector using a generic standard-cell libraryKees van Berkel, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel. 72 [doi]
- Sequencer circuits for VLSI programmingAndrew M. Bailey, Mark B. Josephs. 82-90 [doi]
- A hybrid asynchronous system design environmentC. Farnsworth, David A. Edwards, Jianwei Liu, S. S. Sikand. 91-98 [doi]
- Stretching quasi delay insensitivity by means of extended isochronic forksKees van Berkel, Ferry Huberts, Ad M. G. Peeters. 99 [doi]
- Relative liveness: from intuition to automated verificationRadu Negulescu, Janusz A. Brzozowski. 108-117 [doi]
- Optimised state assignment for asynchronous circuit synthesisChantal Ykman-Couvreur, Bill Lin. 118-127 [doi]
- Hierarchical gate-level verification of speed-independent circuitsOriol Roig, Jordi Cortadella, Enric Pastor. 128-137 [doi]
- Technology mapping of timed circuitsChris J. Myers, Peter A. Beerel, Teresa H. Y. Meng. 138 [doi]
- Testing C-elements is not elementaryJanusz A. Brzozowski, Kaamran Raahemifar. 150-159 [doi]
- Testing self-timed circuits using partial scanAjay Khoche, Erik Brunvand. 160-169 [doi]
- Asynchronous circuits based on multiple localised current-sensing completion detectionEckhard Grass, S. Jones. 170 [doi]
- ECSTAC: a fast asynchronous microprocessorShannon V. Morton, Sam S. Appleton, Michael J. Liebelt. 180-189 [doi]
- Micronets: a model for decentralising control in asynchronous processor architecturesD. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello. 190-199 [doi]
- Hades-towards the design of an asynchronous superscalar processorC. J. Elston, D. B. Christianson, P. A. Findlay, G. B. Steven. 200-209 [doi]
- ARAS: asynchronous RISC architecture simulatorChia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu. 210 [doi]