Antonio J. Acosta, Angel Barriga Barros, Manuel Valencia, Manuel J. Bellido, José L. Huertas. Modeling of real bistables in VHDL. In Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993. pages 460-465, IEEE Computer Society, 1993. [doi]
Abstract is missing.