Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia. Degradation Delay Model Extension to CMOS Gates. In Dimitrios Soudris, Peter Pirsch, Erich Barke, editors, Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Volume 1918 of Lecture Notes in Computer Science, pages 149-158, Springer, 2000. [doi]
Abstract is missing.