Hiroshi Miyashita - researchr alias

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Viewing Publication 1 - 16 from 16

2023

Designing Researchmap: A Revolutionary Scholar Support Platform Achieved Through Human-AI CollaborationNoriko H. Arai, Ryuji Masukawa, Hiroshi Miyashita. ickii 2023: 367-371 [doi]

2021

2017

Automated Historical Fact-Checking by Passage Retrieval, Word Statistics, and Virtual Question-AnsweringMio Kobayashi, Ai Ishii, Chikara Hoshino, Hiroshi Miyashita, Takuya Matsuzaki. ijcnlp 2017: 967-975 [doi]

2016

NUL System at QA Lab-2 TaskMio Kobayashi, Hiroshi Miyashita, Ai Ishii, Chikara Hoshino. ntcir 2016: [doi]

2014

NUL System at NTCIR RITE-VAL TasksAi Ishii, Hiroshi Miyashita, Mio Kobayashi, Chikara Hoshino. ntcir 2014: [doi]

NUL System at QALab TasksHiroshi Miyashita, Ai Ishii, Mio Kobayashi, Chikara Hoshino. ntcir 2014: [doi]

2013

Basis of monitoring central blood pressure and hemodynamic parameters by peripheral arterial pulse waveform analysesHiroshi Miyashita, Shin-ichiro Katsuda. embc 2013: 221-224 [doi]

2007

Efficient Thermal Via Planning for Placement of 3D Integrated CircuitsJing Li, Hiroshi Miyashita. iscas 2007: 145-148 [doi]

2006

Post-placement Thermal Via Planning for 3D Integrated CircuitJing Li, Hiroshi Miyashita. apccas 2006: 808-811 [doi]

Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed HeuristicJing Li, Hiroshi Miyashita. ieicet, 89-A(4):989-995, 2006. [doi]

2005

Equidistance routing in high-speed VLSI layout designYukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi. integration, 38(3):439-449, 2005. [doi]

An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree RepresentationJing Li, Juebang Yu, Hiroshi Miyashita. ieicet, 88-A(12):3398-3404, 2005. [doi]

2004

Equidistance routing in high-speed VLSI layout designYukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi. glvlsi 2004: 220-223 [doi]

1995

Extending pitchmaking algorithms to layouts with multiple grid constraintsHiroshi Miyashita. aspdac 1995: [doi]

1986

An automatic cell pattern generation system for CMOS transistor-pair array LSIHiroshi Miyashita, Tohru Adachi, Kazuhiro Ueda. integration, 4(2):115-133, 1986. [doi]

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