VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes - researchr publication

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Yang Sun, Marjan Karkooti, Joseph R. Cavallaro. VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 2104-2107, IEEE, 2007. [doi]

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