A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range - researchr publication

researchr

You are not signed in
Sign in
Sign up

Adnan Gundel, William N. Carr. A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 3111-3114, IEEE, 2007. [doi]

Abstract is missing.

runs on WebDSL