Adnan Gundel, William N. Carr. A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 3111-3114, IEEE, 2007. [doi]
@inproceedings{GundelC07a, title = {A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range}, author = {Adnan Gundel and William N. Carr}, year = {2007}, doi = {10.1109/ISCAS.2007.378067}, url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378067}, researchr = {https://researchr.org/publication/GundelC07a}, cites = {0}, citedby = {0}, pages = {3111-3114}, booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA}, publisher = {IEEE}, }