Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. Scalable Gate-Level Models for Power and Timing Analysis. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 2938-2941, IEEE, 2007. [doi]
Abstract is missing.