Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. Scalable Gate-Level Models for Power and Timing Analysis. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 2938-2941, IEEE, 2007. [doi]
@inproceedings{BadarogluPWDGM07,
title = {Scalable Gate-Level Models for Power and Timing Analysis},
author = {Mustafa Badaroglu and Geert Van der Plas and Piet Wambacq and Stéphane Donnay and Georges G. E. Gielen and Hugo De Man},
year = {2007},
doi = {10.1109/ISCAS.2007.377865},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.377865},
tags = {analysis},
researchr = {https://researchr.org/publication/BadarogluPWDGM07},
cites = {0},
citedby = {0},
pages = {2938-2941},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA},
publisher = {IEEE},
}