Abstract is missing.
- Single-Event-Upset Trends in Advanced CMOS TechnologiesDavid F. Heidel. [doi]
- Reconfiguration-Based Defect Tolerance for Microfluidic BiochipsKrishnendu Chakrabarty. [doi]
- Adaptive Design for Performance-Optimized RobustnessRamyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka. 3-11 [doi]
- Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-CalibrationTian Xia, Stephen Wyatt, Rupert Ho. 12-19 [doi]
- Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS GatesKristian Granhaug, Snorre Aunet. 20-28 [doi]
- Gate Failures Effectively Shape MultiplexingValeriu Beiu, Walid Ibrahim, Y. A. Alkhawwar, Mawahib H. Sulieman. 29-40 [doi]
- Test Generation for Open Defects in CMOS CircuitsNarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz. 41-49 [doi]
- Implicit Critical PDF Test Generation with Maximal Test EfficiencyKyriakos Christou, Maria K. Michael, Spyros Tragoudas. 50-58 [doi]
- Selecting High-Quality Delay Tests for Manufacturing Test and DebugHangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz. 59-70 [doi]
- Testing Reversible 1D Arrays for Molecular QCAXiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi. 71-79 [doi]
- Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) DesignMinsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park. 80-88 [doi]
- Error Tolerance of DNA Self-Assembly by Monomer Concentration ControlByunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi. 89-97 [doi]
- Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered DefectsYadunandana Yellambalase, Minsu Choi, Yong-Bin Kim. 98-106 [doi]
- A Reconfiguration-based Defect Tolerance Method for Nanoscale DevicesReza M. Rad, Mohammad Tehranipoor. 107-118 [doi]
- Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactorSverre Wichlund, Frank Berntsen, Einar J. Aas. 119-127 [doi]
- A Novel Methodology for Functional Test Data CompressionHamidreza Hashempour, Fabrizio Lombardi. 128-135 [doi]
- Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain ClustersGang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito. 136-144 [doi]
- An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing ConstraintGeewhun Seok, Il-soo Lee, Tony Ambler, B. F. Womack. 145-156 [doi]
- Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoCVijay K. Jain, Glenn H. Chapman. 157-165 [doi]
- Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip CostAkhil Garg, Prashant Dubey. 166-174 [doi]
- Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage SystemsHiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara. 175-183 [doi]
- Modified Triple Modular Redundancy Structure based on Asynchronous Circuit TechniqueRui Gong, Chen Wei, Liu Fang, Kui Dai, Zhiying Wang. 184-196 [doi]
- Low Power SoC Memory BISTYuejian Wu, André Ivanov. 197-205 [doi]
- Synthesis of Efficient Linear Test Pattern GeneratorsAvijit Dutta, Nur A. Touba. 206-214 [doi]
- An Approach to Minimizing Functional ConstraintsAbhijit Jas, Yi-Shing Chang, Sreejit Chakravarty. 215-226 [doi]
- Reliability Evaluation of Repairable/Reconfigurable FPGAsSalvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Adelio Salsano, Fabrizio Lombardi. 227-235 [doi]
- Reliability Analysis of Self-Repairable MEMS AccelerometerXingguo Xiong, Yu-Liang Wu, Wen-Ben Jone. 236-244 [doi]
- Timing Failure Analysis of Commercial CPUs Under Operating StressSanghoan Chang, Gwan Choi. 245-253 [doi]
- Real Time Fault Injection Using Enhanced OCD -- A Performance AnalysisAndré V. Fidalgo, Gustavo R. Alves, José M. Ferreira. 254-264 [doi]
- Combined software and hardware techniques for the design of reliable IP processorsMaurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto. 265-273 [doi]
- Low-Cost Hardening of Image Processing Applications Against Soft ErrorsIlia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara. 274-279 [doi]
- Online hardening of programs against SEUs and SETsCarlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante. 280-290 [doi]
- Equivalent IDDQ Tests for Systems with Regulated Power SupplyChuen-Song Chen, Jien-Chung Lo, Tian Xia. 291-299 [doi]
- Self Testing SoC with Reduced Memory Requirements and Minimized Hardware OverheadOndrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský. 300-308 [doi]
- Bilateral Testing of Nano-scale Fault-tolerant CircuitsLei Fang, Michael S. Hsiao. 309-317 [doi]
- A Metric of Tolerance for the Manufacturing Defects of Threshold Logic GatesSandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas. 318-326 [doi]
- Soft Error Masking Circuit and Latch Using Schmitt Trigger CircuitYoichi Sasaki, Kazuteru Namba, Hideo Ito. 327-335 [doi]
- Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim InterconnectsAjoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier. 336-344 [doi]
- SET Fault Tolerant Combinational Circuits Based on Majority LogicÁ. Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro. 345-352 [doi]
- An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic AlgorithmYusuke Fukushima, Masaru Fukushi, Susumu Horiguchi. 353-361 [doi]
- A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level RedundancyYu-Jen Huang, Da-Ming Chang, Jin-Fu Li. 362-370 [doi]
- Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded MicrocontrollersMarco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano. 371-379 [doi]
- Recovery Mechanisms for Dual Core ArchitecturesChristian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter. 380-388 [doi]
- A Software-Based Error Detection Technique Using Encoded SignaturesYasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli. 389-400 [doi]
- Effective Post-BIST Fault Diagnosis for Multiple FaultsHiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato. 401-109 [doi]
- Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output CharacteristicsYukiya Miura, Jiro Kato. 410-418 [doi]
- Scan-Based Delay Fault Tests for Diagnosis of Transition FaultsIrith Pomeranz, Sudhakar M. Reddy. 419-427 [doi]
- Enhancing Diagnosis Resolution For Delay Faults By Path Extension MethodYing-Yen Chen, Jing-Jia Liou. 428-438 [doi]
- On-Line Mapping of In-Field Defects in Image Sensor ArraysJozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapman, Israel Koren, Zahava Koren. 439-447 [doi]
- Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron TechnologiesMichelle L. La Haye, Cory Jung, David Chen, Glenn H. Chapman, Jozsef Dudas. 448-456 [doi]
- NoC Interconnect Yield Improvement Using Crosspoint RedundancyCristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande. 457-465 [doi]
- Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction codingPartha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu. 466-476 [doi]
- Thermal-Aware SoC Test Scheduling with Test Set Partitioning and InterleavingZhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi. 477-485 [doi]
- Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE CalibrationsFengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi. 486-494 [doi]
- Multi-Site and Multi-Probe Substrate Testing on an ATEXiaojun Ma, Fabrizio Lombardi. 495-506 [doi]
- Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction StreamFederico Rota, Shantanu Dutt, Sahithi Krishna. 507-515 [doi]
- The Filter Checker: An Active Verification Management ApproachJoonhyuk Yoo, Manoj Franklin. 516-524 [doi]
- Effect of Process Variation on the Performance of Phase Frequency DetectorNandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya. 525-534 [doi]
- Data Dependent Jitter Characterization Based on Fourier AnalysisDi Mu, Tian Xia, Hao Zheng. 534-544 [doi]
- A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-CellsLushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya. 545-553 [doi]
- A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural NetworkTadayoshi Horita, Takurou Murata, Itsuo Takanami. 554-562 [doi]
- VLSI Implementation of a Fault-Tolerant Distributed Clock GenerationM. Ferringer, G. Fuchs, A. Steininger, G. Kempf. 563-571 [doi]
- Parity-Based Fault Detection Architecture of S-box for Advanced Encryption StandardMehran Mozaffari Kermani, Arash Reyhani-Masoleh. 572-580 [doi]