H. V. Jayashree - researchr alias

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Viewing Publication 1 - 8 from 8

2018

Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction CircuitsH. V. Jayashree, Sharan Patil, Vinod Kumar Agrawal. jcsc, 27(3):1-28, 2018. [doi]

2017

Reversible circuit optimization using modified toffoli templatesMridula J. Deshpande, H. V. Jayashree, Vinod Kumar Agrawal. icacci 2017: 344-349 [doi]

Reversible circuit design for GCD computation in cryptography algorithmsH. V. Jayashree, Skanda Kotethota, Vinod Kumar Agrawal. ijcta, 45(2):242-259, 2017. [doi]

Efficient Circuit Design of Reversible SquareH. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal. tcos, 29:33-46, 2017. [doi]

2016

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplierH. V. Jayashree, Himanshu Thapliyal, Hamid R. Arabnia, Vinod Kumar Agrawal. tjs, 72(4):1477-1493, 2016. [doi]

2014

Design of Dedicated Reversible Quantum Circuitry for Square ComputationH. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal. vlsid 2014: 551-556 [doi]

2013

Performance Optimization of Flagged BCD AdderNidhi Chandak, H. V. Jayashree, Ghanshyam N. Patil, Nidhi C. Rao. icetet 2013: 183-188 [doi]

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead AdderHimanshu Thapliyal, H. V. Jayashree, A. N. Nagamani, Hamid R. Arabnia. tcos, 17:73-97, 2013. [doi]

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